LTC3606B
13
3606bfb
APPLICATIONS INFORMATION
2. The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is a current
out of V
IN
that is typically much larger than the DC bias
current. In continuous mode, I
GATECHG
= f
O
(Q
T
+ Q
B
),
where Q
T
and Q
B
are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to V
IN
and thus their effects
will be more pronounced at higher supply voltages.
3. I
2
R losses are calculated from the DC resistances of
the internal switches, R
SW
, and external inductor, R
L
.
In continuous mode, the average output current fl ows
through inductor L, but is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R
DS(ON)
and the duty cycle (DC) as
follows:
R
SW
= (R
DS(ON)TOP
) • (DC) + (R
DS(ON)BOT
) • (1– DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
• (R
SW
+ R
L
)
4. Other “hidden” losses, such as copper trace and
internal battery resistances, can account for additional
effi ciency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by making sure that
C
IN
has adequate charge storage and very low ESR at
the switching frequency. Other losses, including diode
conduction losses during dead-time, and inductor
core losses, generally account for less than 2% total
additional loss.
Thermal Considerations
In a majority of applications, the LTC3606B does not
dissipate much heat due to its high effi ciency. In the
unlikely event that the junction temperature somehow
reaches approximately 150°C, both power switches will be
turned off and the SW node will become high impedance.
The goal of the following thermal analysis is to determine
whether the power dissipated causes enough temperature
rise to exceed the maximum junction temperature (125°C)
of the part. The temperature rise is given by:
T
RISE
= P
D
• θ
JA
where P
D
is the power dissipated by the regulator and
θ
JA
is the thermal resistance from the junction of the die
to the ambient temperature. The junction temperature,
T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
As a worst-case example, consider the case when the
LTC3606B is in dropout at an input voltage of 2.7V with
a load current of 800mA and an ambient temperature of
70°C. From the Typical Performance Characteristics graph
of Switch Resistance, the R
DS(ON)
of the switch is 0.33.
Therefore, the power dissipated is:
P
D
= I
OUT
2
• R
DS(ON)
= 212mV
Given that the thermal resistance of a properly soldered
DFN package is approximately 40°C/W, the junction
temperature of an LTC3606B device operating in a 70°C
ambient temperature is approximately:
T
J
= (0.212W • 40°C/W) + 70°C = 78.5°C
which is well below the absolute maximum junction
temperature of 125°C.
