CU40045-UW1J
6
9.2 Display Clear
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 1 01H
RS=0
This instruction
1. Fills all locations in the display data (DD) RAM with 20H (Blank character).
2. Clears the contents of the address counter to 0H.
3. Sets the display for zero character shift.
4. Sets the address counter to point to the DD RAM.
5. If the cursor is displayed, the cursor moves to the left most character in the top line
(line 1 ).
6. Sets the address counter to increment on each access of DD RAM or CG RAM.
9.3 Cursor Home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 1
*
02H to 03H
RS=0
*: don't care
This instruction
1. Clears the contents of the address counter to 0H.
2. Sets the address counter to point to the DDRAM.
3. Sets the display for zero character shift.
4. If the cursor is displayed, moves the left most character in the top line (line 1).
9.4 Entry Mode Set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 1 I/D S 04H to 07H
RS=0
The I/D bit selects the way in which the contents of the address counter are modified after every
access to DDRAM or CGRAM.
I/D=1: The address counter is increment.
I/D=0: The address counter is decrement.
The S bit enables display shifts instead of cursor shift, after each write or read to the DDRAM.
S=1: Display shift enabled.
S=0: Cursor shift enabled.
The direction in which the display is shifted is opposite in sense to that of the cursor. For
example if S=0 and I/D=1, the cursor would shift one character to the right after a CPU writes
to DD RAM. However if S=1 and I/D=1, the display would shift one character to the left and
the cursor would maintain its position on the panel.