19
LT1507
APPLICATIONS INFORMATION
WUU
U
move around, but at the same time phase moves with it so
that adequate phase margin is maintained over a very wide
range of ESR (≥ 5:1)
Undervoltage Lockout
See Application Information in LT1376 data sheet.
N8 0695
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.015
(0.380)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
12
3
4
876
5
0.255 ± 0.015*
(6.477 ± 0.381)
0.400*
(10.160)
MAX
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325
+0.025
–0.015
+0.635
–0.381
8.255
()
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
components. In many cases only C
C
is needed. Adding R
C
will improve phase margin, but this may necessitate the need
for C
F
to limit switching frequency ripple at the V
C
pin.
In Figure 10, full loop phase/gain characteristics are shown
with a compensation capacitor (C
C
) of 0.0033µF, giving the
error amplifier a pole at 240Hz, with phase rolling off to 90°
and staying there. The overall loop has a gain of 77dB at low
frequency rolling off to unity gain at 20kHz. Phase shows a
2-pole characteristic until the ESR of the output capacitor
brings it back above 10kHz. Phase margin is about 60° at
unity-gain.
Analog experts will note that around 1kHz, phase dips to
within 20° of the zero phase margin line. This is typical of
switching regulators because of the 2-pole rolloff generated
by the output capacitor and the compensation network. This
region of low phase is not a problem as long as it does not
occur near unity-gain. In practice, the variability of output
capacitor ESR tends to dominate all other effects with respect
to loop response. Variations in ESR
will
cause unity-gain to
FREQUENCY (kHz)
LOOP GAIN (dB)
LOOP PHASE (°C)
80
60
40
20
0
–20
200
150
100
50
0
–50
0.01 10.1 10 100 100
LT1511 • F10
V
IN
= 10V
V
OUT
= 5V, I
OUT
= 500mA
C
OUT
= 100µF, 10V, AVX TPS
C
C
= 3.3nF, R
C
= 0
L = 10µH
GAIN
PHASE
Figure 10. Overall Loop Phase and Gain
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
U
