16
LT1507
APPLICATIONS INFORMATION
WUU
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The circuit in Figure 6 will allow operation at light loads
with low input voltages. It uses a small PNP to charge the
boost capacitor (C2) and an extra diode (D3) to complete
the power path
from V
SW
to the boost capacitor. Note that
the diodes have been changed to Schottky BAT85s to
optimize low voltage operation. Figure 5 shows that with
the added PNP, minimum load current can be reduced to
6mA and still guarantee proper start-up with 4.7V input.
problems. For low input voltage, high sync frequency
applications, the circuit shown in Figure 7 can be used to
generate an external slope compensation ramp that elimi-
nates subharmonic oscillation. See Frequency Compen-
sation section for a discussion of an entirely different
cause of subharmonic switching before assuming that the
cause is insufficient slope compensation. Application Note
19 has more details on the theory of slope compensation.
V
IN
V
SW
SENSE
BOOST
GND V
C
LT1507-3.3
D2
BAT85
C2
0.22µF
L1
D1
1N5818
C
C
+
C1
+
INPUT
LT1507 • F06
D3
BAT85
Q1
2N3906
V
OUT
= 3.3V
Figure 6. Adding a Small PNP to Reduce Minimum
Start-Up Voltage
SYNCHRONIZING
The LT1507 SYNC pin is used to synchronize the internal
oscillator to an external signal. It is directly logic compat-
ible and can be driven with any signal between 10% and
90% duty cycle. The synchronizing range is equal to
initial
operating frequency up to 1MHz (above 700kHz external
slope compensation may be needed). This means that
minimum practical sync frequency is equal to the worst-
case
high
self-oscillating frequency (560kHz) not the
typical operating frequency of 500kHz. Caution should be
used when synchronizing above 700kHz because at higher
sync frequencies, the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice the output voltage and
shows up as alternating pulse widths at the switch node.
It does not cause the regulator to lose regulation, but
switch frequency content down to 100kHz may be objec-
tionable. Higher inductor values will tend to eliminate
SYNC
V
SW
GND V
C
LT1507
+
V
OUT
LT1507 • F07
R
C
470Ω
R
S
5.2k
C
S
1000pF
C
C
2000pF
Figure 7. Adding External Slope Compensation for High
Sync Frequencies
External Slope Compensation Ramp
The LT1507 is a current mode switching regulator and
therefore, it requires something called “slope compensa-
tion”
when operated above 50% duty cycle in continuous
mode.
This condition occurs when input voltage is less
than twice output voltage. Slope compensation adds a
ramp to the switch current sense signal generated on the
chip during switch ON time. Typically the ramp is gener-
ated from a portion of the internal oscillator waveform. In
the LT1507, the ramp is arranged to be zero until the
oscillator waveform reaches about 40% of its final value.
This minimizes the total amount of ramp added to switch
current. The reason for doing it this way is that the ramp
subtracts from switch current limit, so that switch current
limit would be considerably lower at high duty cycle
compared to low duty cycle if the ramp existed at all duty
cycles. By starting the ramp at the 40% point, changes in
current limit are minimized. No ramp is needed when
operating below 50% duty cycle.
Problems can occur with this technique if the regulator is
used with a combination of high external sync frequency
and more than 50% duty cycle. The basic sync function
