ISL95310UIU10Z

4
FN8083.1
August 27, 2015
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 1) MAX UNIT
I
CC1
V
CC
supply current, volatile write/read CS = V
IL
, U/D = V
IL
or V
IH
and INC = 0.4V/2.4V
min; t
CYC
R
L
, R
H
, R
W
not connected
1mA
I
CC2
V
CC
supply current, nonvolatile write CS = V
IL
, U/D = V
IL
or V
IH
and INC = 0.4V/2.4V
min; t
CYC
R
L
, R
H
, R
W
not connected
3mA
I
SB
V
CC
current, standby V
CC
= +5.5V, 2-wire interface in standby state 5 µA
V
CC
= +3.6V, 2-wire interface in standby state 2 µA
I
V+
V+ bias current V+ = 13.2V; V
CC
= +5.5V 1 µA
I
LkgDig
Leakage current, at pins INC, CS,
U/D
, A0, and A1 pins
Voltage at pin from GND to V
CC
-10 10 µA
I
LI
CS input leakage current V
IN
= V
CC
±1 µA
V
CC
= 3V, CS = 0 60 100 150 µA
V
CC
= 5V, CS = 0 120 200 250 µA
I
V+
V+ bias current V+ = 13.2V; V
CC
= +5.5V 1 µA
t
DCP
(Note 13)
DCP wiper response time INC
falling edge of last bit of DCP data byte to
wiper change
s
Vpor
(Note 13)
Power-on recall voltage Minimum V
CC
at which memory recall occurs 1.8 2.6 V
V
CC
Ramp
(Note 13)
V
CC
ramp rate 0.2 V/ms
t
D
(Note 13)
Power up delay V
CC
above Vpor, to DCP initial value register
recall completed, and 2-wire Interface in standby
state
3ms
EEPROM SPECS
EEPROM endurance 150,000 Cycles
EEPROM retention Temperature 75°C 50 Years
SERIAL INTERFACE SPECS
V
IL
INC, CS, and U/D -0.3 0.3*
V
CC
V
V
IH
INC, CS, and U/D 0.7*
V
CC
V
CC
+
0.3
V
Hysteresis
(Note 13)
INC
, CS, and U/D input buffer
hysteresis
0.05*
V
CC
V
Cpin
(Note 13)
INC
, CS, and U/D pin capacitance 10 pF
AC Electrical Specifications V
CC
= 5V ±10%, T
A
= Full Operating Temperature Range unless otherwise stated
SYMBOL PARAMETER MIN
TYP
(Note 4) MAX UNIT
t
Cl
CS to INC setup 100 ns
t
lD
(Note 13) INC HIGH to U/D change 100 ns
t
DI
(Note 13) U/D to INC setup 1 µs
t
lL
INC LOW period 1 µs
t
lH
INC HIGH period 1 µs
t
lC
INC inactive to CS inactive 1 µs
ISL95310
5
FN8083.1
August 27, 2015
Symbol Table
t
CPHS
CS deselect time (STORE) 20 ms
t
CPHNS
(Note 13) CS deselect time (NO STORE) 1 µs
t
IW
(Note 13) INC to R
W
change 100 500 µs
t
CYC
INC cycle time 4 µs
t
R,
t
F
(Note 13) INC input rise and fall time 500 µs
NOTES:
1. Typical values are for T
A
= 25°C and 3.3V supply voltage.
2. LSB: [V(R
W
)
127
– V(R
W
)
0
]/127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(R
W
)
0
/LSB.
4. FS error = [V(R
W
)
127
– V+]/LSB.
5. DNL = [V(R
W
)
i
– V(R
W
)
i-1
]/LSB-1, for i = 1 to 127. i is the DCP register setting.
6. INL = V(R
W
)
i
– (i • LSB – V(R
W
)
0
) for i = 1 to 127.
7.
for i = 16 to 120 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper
voltage over the temperature range.
8. MI =
|R
127
– R
0
| /127. R
127
and R
0
are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.
9. Roffset = R
0
/MI, when measuring between R
W
and R
L
.
Roffset = R
127
/MI, when measuring between R
W
and R
H
.
10. RDNL = (R
i
– R
i-1
)/MI, for i = 16 to 127.
11. RINL = [R
i
– (MI • i) – R
0
]/MI, for i = 16 to 127.
12.
for i = 16 to 127, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.
13. This parameter is not 100% tested.
14. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a
valid STOP condition at the end of a Write sequence of a 3-wire serial interface Write operation, to the end of the self-timed internal non-volatile
write cycle.
AC Electrical Specifications V
CC
= 5V ±10%, T
A
= Full Operating Temperature Range unless otherwise stated (Continued)
SYMBOL PARAMETER MIN
TYP
(Note 4) MAX UNIT
TC
V
Max V RW
i
Min V RW
i

Max V RW
i
Min V RW
i
+2§
-------------------------------------------------------------------------------------------------x
10
6
125°C
-----------------=
TC
R
Max RiMin Ri
Max RiMin Ri+2§
------------------------------------------------------------------
10
6
125°C
-----------------
=
WAVEFORM INPUTS OUTPUTS
Must be steady Will be steady
May change from Low to High Will change from Low to High
Will change from High to Low
Don’t Care: Changes Allowed Changing: State Not Known
N/A
Center Line is High Impedance
May change from High to Low
ISL95310
6
FN8083.1
August 27, 2015
A.C. Timing
Power Up and Down Requirements
In order to prevent unwanted tap position changes, or an
inadvertent store, bring the CS
and INC high before or
concurrently with the V
CC
pin on power-up. The
potentiometer voltages must be applied after this sequence
is completed. During power-up, the data sheet parameters
for the DCP do not fully apply until 1ms after V
CC
reaches its
final value. The V
CC
ramp spec is always in effect.
Pin Descriptions
R
H
and R
L
The high (R
H
) and low (R
L
) terminals of the ISL95310 are
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of R
L
and R
H
references the
relative position of the terminal in relation to wiper movement
direction selected by the U/D
input and not the voltage
potential on the terminal.
R
W
R
W
is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D
input.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS
is returned HIGH while the INC input is also HIGH. After
the store operation is complete the ISL95310 will be placed
in the low power standby mode until the device is selected
once again.
Principles of Operation
There are three sections of the ISL95310: the input control,
counter and decode section; the nonvolatile memory; and
the resistor array. The input control section operates just like
an up/down counter. The output of this counter is decoded to
turn on a single electronic switch connecting a point on the
resistor array to the wiper output. Under the proper
conditions the contents of the counter can be stored in
nonvolatile memory and retained for future use. The resistor
array is comprised of 127 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for t
IW
(INC to V
W
change). The
R
TOTAL
value for the device can temporarily be reduced by
a significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
CS
INC
U/D
R
W
t
CI
t
IL
t
IH
t
CYC
t
ID
t
DI
t
IW
MI
(3)
t
IC
t
CPHS
t
F
t
R
10%
90% 90%
t
CPHNS
ISL95310

ISL95310UIU10Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs SPI 128 POSITION NON VOLATILE DCP 50 KOHM
Lifecycle:
New from this manufacturer.
Delivery:
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