2.8 Fast Detect Mode
In many applications, it is desirable to sense touch at high
speed. Examples include scrolling ‘slider’ strips or ‘Off’
buttons. It is possible to place the device into a ‘Fast Detect’
mode that usually requires under 15ms to respond. This is
accomplished internally by setting the Detect Integrator to
only two counts, i.e. only two successive detections are
required to detect touch.
In LP mode, ‘Fast’ detection will not speed up the initial
delay (which could be up to 360ms typical depending on the
option setting). However, once a key is detected the device
is forced back into normal speed mode. It will remain in this
faster mode until another LP pulse is received.
When used in a ‘slider’ application, it is normally desirable to
run the keys without AKS.
In both normal and ‘Fast’ modes, the time required to
process a key release is the same: it takes six sequential
confirmations of non-detection to turn a key off.
Fast Detect mode can be enabled as shown in Tables 1.2
and 1.6.
2.9 Simplified Mode
A simplified operating mode which does not require the
majority of option resistors is available. This mode is set by
connecting a resistor labeled SMR between pins SNS6K and
SNS7. (see Figure 1.2).
In this mode there is only one option available - AKS enable
or disable. When AKS is disabled, Fast Detect mode is
enabled; when AKS is enabled, Fast Detect mode is off.
AKS in this mode is global only (i.e. operates across all
functioning keys).
The other option features are fixed as follows:
DETECT Pin: Push-pull, active high
SYNC/LP Function: LP mode, ~200ms response time
Max On-Duration: 60 seconds
See also Tables 1.6 and 1.7.
2.10 Unused Keys
Unused keys should be disabled by removing the
corresponding Cs, Rs, and Rsns components and
connecting SNS pins as shown in the ‘Unused’ column of
Table 1.1. Unused keys are ignored and do not factor into
the AKS function (Section 2.6).
2.11 Serial 1W Interface
The 1W serial interface is an RS-232 based auto baud rate
serial asynchronous interface that requires only one wire
between the host MCU and the QT1101. The serial data are
extremely short and simple to interpret.
Auto baud rate detection takes place by having the host
device send a specific character to the QT1101, which
allows the QT1101 to set its baud rate to match that of the
host.
One feature of this method is that the baud rate can be any
rate between 8,000 and 38,400 bits per second. Neither the
QT1101 nor the host device has to be accurate in their
transmission rates, i.e. crystal control is not required.
Depending on the timing of a 1W host transmission, the
QT1101 device may need to abort an acquisition burst, and
rerun it after the transmission is complete and a reply has
been sent. As a consequence, each host request can
potentially result in a small, unnoticeable increase in
detection delay.
1W Connection: The 1W pin should be pulled high with a
resistor. When not in use it floats high, hence this causes no
increase in supply current.
During transmission from the host, the host may drive the
1W line with either an open-drain or a push-pull driver.
However, if the host uses push-pull driving, it must release
the 1W line as soon as it is done with its stop bit so that
there is no drive conflict when the QT1101 sends its reply.
If open-drain transmission is used by the host, the value of
the pull-up resistor should be optimized for the desired baud
rate: faster rates require a lower value of resistor to prevent
rise-time problems. A typical value for 19,200 baud might be
100K. An oscilloscope should be used to confirm that the
resistor is not causing excessive timing skew that might
cause bit errors.
The QT1101 uses push-pull drive to transmit
data out on the 1W line back to the host. When
the stop bit level is established, 1W is floated;
for this reason, a pull-up resistor should always
be used on the 1W pin to prevent the signal from
drifting to an undefined state. A 100K pull-up
resistor on 1W is recommended, unless the host
uses open-drain drive to the QT1101, in which
case a lower value may be required (see prior
paragraph).
2.11.1 Basic 1W Operation
The basic sequence of 1W serial operation is
shown in Figure 2.1. The 1W line is bi-directional
and must be pulled high with a resistor to
prevent a floating, undefined state (see previous
section).
Lq
7 QT1101 R4.06/0806
Figure 2.1 Basic 1W Sequence
*See Figure 2.3
Figure 2.2 1W UART Host Pattern
1 ~ 3 bit periods
1W
/CHANGE
key state
change
request
from host
(1 byte)
d
r
i
ven rep
l
y
from QT1101
(2 bytes)*
floating floating
floating floating
S01234 7S
Serial bits
56
1W
(from host)
Oscillator Tolerance: While
the auto baud rate detection
mechanism has a wide
tolerance for oscillator error,
the QT’s oscillator should still
not vary by more than
±
20%
from the recommended value.
Beyond a 20% error,
communications at either the
lower or upper stated limits
could fail. The oscillator
frequency can be checked
with an oscilloscope by
probing the pulse width on
the SNS lines; these should ideally be 2.15µs in width each
at the beginning of a burst with the recommended
spread-spectrum circuit, or 2µs wide if no spread-spectrum
circuit is used.
Host Request Byte: The host requests the key state from
the QT1101 by sending an ASCII "P" character (ASCII
decimal code 80, hex 0x50) over the 1W line. The character
is formatted according to conventional RS-232:
8 data bits
no parity
1 stop bit
baud rate: 8,000 - 38,400
Figure 2.2 shows the bit pattern of the host request byte
(‘P’). The first bit labeled ‘S’ is the start bit, the last ‘S’ is the
stop bit. This bit pattern should never be changed. The
QT1101 will respond at the same baud rate as the received
‘P’ character.
After sending the ‘P’ character the host must immediately
float the 1W signal to prevent a drive conflict between the
host and the QT1101 (see Figure 2.1). The delay from the
received stop bit to the QT1101 driving the 1W pin is in the
range 1-3 bit periods, so the host should float the pin within
one bit period to prevent a drive conflict.
Data Reply: Before sending a reply, the QT1101 returns the
/CHANGE signal to its inactive (float-high) state.
The QT1101 then replies by sending two eight-bit characters
to the host over the 1W line using the same baud rate as the
request. With no keys pressed, both repl y bytes are ASCII
‘@’ (0x40) characters; any keys that are pressed at the time
of the reply result in their associated bits being set in the
reply. Figure 2.3 shows the reply bytes when keys 0, 2 and 7
are pressed - 0x45, 0x42, and the associations between
keys and bits in the reply.
The QT1101 floats the 1W pin again after establishing the
level of the stop bit.
2.11.2 LP Mode Effects on 1W
The use of low power (LP) mode
presents some additional 1W timing
requirements. In LP mode (Section
2.5), the QT1101 will only respond to
a request from the host when it is
making one of its infrequent checks
for a key press. Hence, in that
condition most requests from the host
to the QT1101 will be ignored, since
the QT1101 will be sleeping and
unresponsive. However, if either
/CHANGE or DETECT are active the
QT1101 will be at full speed, and hence will always respond
to ‘P’ requests.
Note that when sleeping in LP mode, there are by definition
no keys active, so there should not be a reason for the host
to send the ‘P’ query command in the first place.
Three strategies are available to the host to ensure that LP
mode operates correctly:
# /CHANGE used. The host monitors /CHANGE, and only
sends a ‘P’ request when it is low. The part is awake by
definition when /CHANGE is low. If /CHANGE is high,
key states are known to be unchanged since the last
reply received from the QT1101, and so additional ‘P’
requests are not needed. Before triggering LP mode the
host should wait for /CHANGE to go high after all keys
have become inactive.
# DETECT used. The host monitors DETECT, and if it is
active (i.e. the part is awake) it polls the device regularly
to obtain key status. When DETECT is inactive (the part
may be sleeping) no requests are sent because it is
known that no keys are active. Before triggering LP
mode the host should wait for DETECT to become
inactive, and then send one additional 'P' request to
ensure /CHANGE is also made inactive.
# Neither /CHANGE nor DETECT used. The host polls
the device regularly to obtain key status, with a timeout
in operation when awaiting the reply to each ‘P’ request.
Not receiving a reply within the timeout period only
occurs when the part is sleeping, and hence when no
keys are active. Before triggering LP mode the host
should wait for all keys to become inactive and then
send an additional 'P' request to the QT1101 to ensure
/CHANGE is also inactive.
2.11.3 2W Operation
1W operation, as described above, requires that the host
float the 1W line while awaiting a reply from the QT1101; this
is not always possible.
Lq
8 QT1101 R4.06/0806
Figure 2.3 UART Response Pattern on 1W Pin
(Shown with keys 0, 2 and 7 detecting) * Fixed bit values
U - Unused bits
S01234567 S01234567S
012345
**
6789UU
**
Serial bits
Associated key #
1W
(from QT1101)
S
floating
floating
floating
Figure 2.4 2W Operation
1W
(from QT1101)
/CHANGE
RX
(from host)
key state
change
request
from host
(1 byte)
d
r
i
ven rep
l
y
from QT1101
(2 bytes)
floating floating
floating floating
1 ~ 3 bit periods
To solve this problem, the QT1101 can also receive the ‘P’
character from the host on its ‘Rx’ pin separately from the
1W pin (Figure 2.4). The host need not float the Rx line since
the QT1101 will never try to drive it.
Following a ‘P’ on Rx, the QT1101 will send the same
response pattern (Figure 2.3) over the 1W line as in pure 1W
mode.
All other comments and timings given for 1W operation are
applicable for 2W operation. LP operation is the same for
2W mode as for 1W.
If the Rx pin is not used, it must be tied to Vdd.
3 Design Notes
3.1 Oscillator Frequency
The QT1101’s internal oscillator runs from an external
network connected to the OSC and SS pins as shown in
Figures 1.1 and 1.2. The charts in these figures show the
recommended values to use depending on nominal
operating voltage and spread spectrum mode.
If spread spectrum mode is not used, only resistor Rb1
should be used, the Css capacitor eliminated, and the SS
pin pulled to Vss with a 100K resistor.
An out-of-spec oscillator can induce timing problems such as
large variations in Max On-Duration times and response
times as well as on the serial port.
Effect on serial communications: The oscillator frequency
has no nominal effect on serial communications since the
baud rate is set by an auto-sensing mechanism. However, if
the oscillator is too far outside the recommended settings,
the possible range of serial communications can shrink. For
example, if the oscillator is too slow, the upper baud rate
range can be reduced.
The burst pulses should always be in the range of 1.8-2.4µs
at the start of a burst to allow the serial port to operate at its
specified limits; in spread-spectrum mode, the first pulses of
a burst should ideally be 2.15µs. In non spread-spectrum
mode, the target value is 2µs. If in doubt, make the pulses
on the narrower side (i.e. a faster oscillator) when using the
higher baud rates, and conversely on the wider side when
using the lowest baud rates.
3.2 Spread Spectrum Circuit
The QT1101 offers the ability to spectrally spread its
frequency of operation to heavily reduce susceptibility to
external noise sources and to limit RF emissions. The SS pin
is used to modulate an external passive RC network that
modulates the OSC pin. OSC is the main oscillator current
input. The circuits and recommended values are shown in
Figures 1.1 and 1.2.
The resistors Rb1 and Rb2 should be changed depending
on Vdd. As shown in Figures 1.1 and 1.2, three sets of
values are recommended for these resistors depending on
Vdd. The power curves in Section 4.6 also show the effect of
these resistors.
The spread-spectrum circuit can be eliminated if it is not
desired (see Section 3.1). Non spread-spectrum mode
consumes significantly less current in one of the LP modes.
The spread-spectrum RC network might need to be modified
slightly with longer burst lengths. The sawtooth waveform
observed on SS should reach a crest height as follows:
Vdd >= 3.6V: 17% of Vdd
Vdd < 3.6V: 20% of Vdd
The Css capacitor connected to SS (Figures 1.1 and 1.2)
should be adjusted so that the waveform approximates the
above amplitude, ±10%, during normal operation in the
target circuit. If this is done, the circuit will give a spectral
modulation of 12-15%.
3.3 Cs Sample Capacitors - Sensitivity
The Cs sample capacitors accumulate the charge from the
key electrodes and determine sensitivity. Higher values of Cs
make the corresponding sensing channel more sensitive.
The values of Cs can differ for each channel, permitting
differences in sensitivity from key to key or to balance
unequal sensitivities. Unequal sensitivities can occur due to
key size and placement differences and stray wiring
capacitances. More stray capacitance on a sense trace will
desensitize the corresponding key; increasing the Cs for that
key will compensate for the loss of sensitivity.
The Cs capacitors can be virtually any plastic film or low to
medium-K ceramic capacitor. The ‘normal’ Cs range is 2 .2nF
to 50nF depending on the sensitivity required; larger values
of Cs require better quality to ensure reliable sensing.
Acceptable capacitor types for most uses include PPS film,
polypropylene film, and NP0 and X7R ceramics. Lower
grades than X7R are not advised.
The required values of Cs can be noticeably affected by the
presence and connection of the option resistors.
3.4 Power Supply
The power supply can range from 2.8V to 5.0V. If this
fluctuates slowly with temperature, the device will track and
compensate for these changes automatically with only minor
changes in sensitivity. If the supply voltage drifts or shifts
quickly, the drift compensation mechanism will not be able to
keep up, causing sensitivity anomalies or false detections.
The power supply should be locally regulated using a
three-terminal device, to between 2.8V and 5.0V. If the
supply is shared with another electronic system, care should
be taken to ensure that the supply is free of digital spikes,
sags, and surges which can cause adverse effects.
For proper operation a 0.1µF or greater bypass capacitor
must be used between Vdd and Vss. The bypass capacitor
should be routed with very short tracks to the device’s Vss
and Vdd pins.
3.5 PCB Layout and Construction
Refer to Quantum application note AN-KD02 for information
related to layout and construction matters.
Lq
9 QT1101 R4.06/0806

QT1101-IS48G

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
Interface - Specialized Integrated Circuit
Lifecycle:
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