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DFLT220A-7

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2016
October, 2016 − Rev. 3
1 Publication Order Number:
ESD7104/D
ESD7104
Transient Voltage
Suppressors
Low Capacitance ESD Protection for
High Speed Data
The ESD7104 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The flow−through style
package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines such as USB 3.0 and HDMI.
Features
• Low Capacitance (0.3 pF Typical, I/O to GND)
• Low ESD Clamping Voltage
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• UL Flammability Rating of 94 V−0
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• USB 3.0
• eSATA 3.0
• Thunderbolt (Light Peak)
• HDMI 1.3/1.4
• Display Port
MAXIMUM RATINGS (T
J
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Operating Junction Temperature Range T
J
−55 to +125 °C
Storage Temperature Range T
stg
−55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
MARKING
DIAGRAM
Device Package Shipping
ORDERING INFORMATION
UDFN10
CASE 517BB
PIN CONFIGURATION
AND SCHEMATIC
www.
onsemi.com
ESD7104MUTAG UDFN10
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
7M MG
G
7M = Specific Device Code (tbd)
M = Date Code
G = Pb−Free Package
I/O I/O I/OI/O GND
N/C N/C N/C N/CGND
14523
10 7 698
(Note: Microdot may be in either location)
GND
Pin 2 Pin 4 Pin 5Pin 1
=
I/O I/O I/OI/O
Pin 3
SZESD7104MUTAG UDFN10
(Pb−Free)
3000 / Tape &
Reel
ESD7104
www.onsemi.com
2
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise specified)
Parameter
Symbol Conditions Min Typ Max Unit
Reverse Working Voltage V
RWM
I/O Pin to GND 5.0 V
Breakdown Voltage V
BR
I
T
= 1 mA, I/O Pin to GND 5.5 V
Reverse Leakage Current I
R
V
RWM
= 5 V, I/O Pin to GND 1.0
mA
Clamping Voltage (Note 1) V
C
I
PP
= 1 A, I/O Pin to GND (8 x 20 ms pulse)
10 V
Clamping Voltage (Note 2) V
C
IEC61000−4−2, ±8 KV Contact See Figures 1 and 2 V
Clamping Voltage (Note 3) V
C
I
PP
= ±8 A
I
PP
= ±16 A
14.1
19.5
V
Junction Capacitance C
J
V
R
= 0 V, f = 1 MHz between I/O Pins 0.2 0.3 pF
Junction Capacitance C
J
V
R
= 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.35 pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Surge current waveform per Figure 5.
2. For test procedure see Figures 3 and 4 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − 2008 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50 W, t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
Figure 1. IEC61000−4−2 +8 KV Contact
Clamping Voltage
Figure 2. IEC61000−4−2 −8 KV Contact
Clamping Voltage
TIME (ns)
120100806040200−20
−10
0
10
20
30
40
50
60
VOLTAGE (V)
140
70
80
TIME (ns)
120100806040200−20
−80
−70
−60
−50
−40
−30
−20
−10
VOLTAGE (V)
140
0
10
ESD7104
www.onsemi.com
3
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
I
peak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Figure 4. Diagram of ESD Clamping Voltage Test Setup
50 W
50 W
Cable
TVS
Oscilloscope
ESD Gun
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 5. 8 X 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0
020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
t
P
t
r
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE I
RSM
@ 8 ms
HALF VALUE I
RSM
/2 @ 20 ms
P1-P3P4-P6P7-P9

DFLT220A-7

Mfr. #:
Buy DFLT220A-7
Manufacturer:
Diodes Incorporated
Description:
TVS Diodes / ESD Suppressors 225W 5.0V to 220V SM Trans Suppressor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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