1. General description
The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop.
The device features clock (CP) and master reset (MR
) inputs. The outputs Qn assume the
state of their corresponding Dn inputs that meet the set-up and hold time requirements on
the LOW-to-HIGH clock (CP) transition. A LOW on MR
forces the outputs LOW
independently of clock and data inputs. Inputs include clamp diodes which enable the use
of current limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC273-Q100: CMOS level
For 74HCT273-Q100: TTL level
Common clock and master reset
Eight positive edge-triggered D-type flip-flops
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
3. Ordering information
74HC273-Q100; 74HCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 1 — 19 June 2013 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC273D-Q100 40 C to +125 C SO20 plastic small outline package; 20 leads; body width
7.5 mm
SOT163-1
74HCT273D-Q100
74HC273PW-Q100 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74HCT273PW-Q100
74HC273BQ-Q100 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
74HCT273BQ-Q100
