74HC_HCT273_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 19 June 2013 3 of 19
NXP Semiconductors
74HC273-Q100; 74HCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
Fig 4. Logic diagram
001aae056
D
R
D
Q
FF8
Q7
D7
D
R
D
Q
FF7
Q6
D6
D
R
D
Q
FF6
Q5
D5
D
R
D
Q
FF5
Q4
D4
D
R
D
Q
FF4
Q3
D3
D
R
D
Q
FF3
Q2
D2
D
R
D
Q
FF2
Q1
D1
D
CPCPCPCP
CPCPCPCP
R
D
Q
FF1
Q0
D0
CP
MR
74HC_HCT273_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 19 June 2013 4 of 19
NXP Semiconductors
74HC273-Q100; 74HCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20
DDD
+&4
+&74
7UDQVSDUHQWWRSYLHZ
4
'
4
'
' '
4 4
4 4
' '
' '
4 4
*1'
&3
05
9
&&











WHUPLQDO
LQGH[DUHD
*1'

Table 2. Pin description
Symbol Pin Description
MR
1 master reset input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 flip-flop output
D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input
GND 10 ground (0 V)
CP 11 clock input (LOW-to-HIGH, edge-triggered)
V
CC
20 supply voltage
74HC_HCT273_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 19 June 2013 5 of 19
NXP Semiconductors
74HC273-Q100; 74HCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 package: above 70 C the value of P
tot
derates linearly with 8 mW/K.
For TSSOP20 package: above 60 C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN20 package: P
tot
derates linearly with 4.5 mW/K above 60 C.
Table 3. Function table
[1]
Operating modes Inputs Outputs
MR CP Dn Qn
reset (clear) L X X L
load “1” H hH
load “0” H lL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5V
[1]
- 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V
[1]
- 20 mA
I
O
output current 0.5 V < V
O
< V
CC
+0.5V - 25 mA
I
CC
supply current - 50 mA
I
GND
ground current 50 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[2]
- 500 mW

74HCT273PW-Q100J

Mfr. #:
Manufacturer:
Nexperia
Description:
Flip Flops Octal Dtype flipflop positive-edgetrigger
Lifecycle:
New from this manufacturer.
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