2004 Apr 07 2
Philips Semiconductors Product specification
Octal D-type registered transceiver; 3-state 74LVC543A
FEATURES
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Supply voltage range from 1.2 V to 3.6 V
• Complies with JEDEC standard JESD8-B/JESD36
• CMOS low-power consumption
• Direct interface with TTL levels
• 8-bit octal transceiver with D-type latch
• Back-to-back registers for storage
• Separate controls for data flow in each direction
• 3-state non-inverting outputs for bus oriented
applications
• High-impedance when V
CC
=0V
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
DESCRIPTION
The 74LVC543A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The 74LVC543A is an octal registered transceiver
containing two sets of D-type latches for temporary
storage of the data flow in either direction. Separate latch
enable inputs (pins LE
AB
and LE
BA
) and output enable
inputs (pins OE
AB
and OE
BA
) are provided for each
register to permit independent control of inputting and
outputting in either direction of the data flow.
The 74LVC543A contains eight D-type latches, with
separate inputs and controls for each set. For data flow
from pins A to B, for example, the A to B enable input
(pin E
AB
) must be LOW in order to enter data from pins
A0 to A7 or take data from pins B0 to B7, as indicated in
the “Function table”. With pin E
AB
LOW, a LOW signal on
the A to B latch enable input (pin LE
AB
) makes the A to B
latches transparent; a subsequent LOW-to-HIGH
transition on pin LE
AB
puts the A data into the latches
where it is stored and the B outputs no longer change with
the A inputs. With pins E
AB
and OE
AB
both LOW, the
3-state B output buffers are active and display the data
present at the outputs of the A latches.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
≤ 2.5 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL
/t
PLH
propagation delay An to Bn; Bn to An C
L
= 50 pF; V
CC
= 3.3 V 3.0 ns
C
I
input capacitance 4.0 pF
C
I/O
input/output capacitance 5.0 pF
C
PD
power dissipation capacitance per latch V
CC
= 3.3 V; notes 1 and 2
outputs enabled 15.0 pF
outputs disabled 3.0 pF
