LTC3458
13
3458fa
rolled off before the RHP zero frequency.
The typical error amp compensation is shown in Figure 2.
The equations for the loop dynamics are as follows:
f
eCC
which is close to DC
f
RCC
f
RCC
POLE
ZERO
Z
POLE
Z
1
6
1
2
1
210 1
1
21
1
22
=
π
π
π
••
••
••
+
7
8
COMP
FB
ERROR
AMP
1.25V
V
OUT
R1
R2
CC1
CC2
R
Z
3458 F01
Figure 2
APPLICATIO S I FOR ATIO
WUUU
LTC3458
14
3458fa
TYPICAL APPLICATIO S
U
V
IN
GND/PGND
SHDN
SYNC
R
T
I
LIM
SW
V
OUT
FB
COMP
SS
BURST
LTC3458
Li-Ion
2.5V to 4.2V
2.2μF
WURTH
12μH
774775112
ON OFF
243k 124k 133k
324k
33k
0.01μF
0.01μF
560pF
10pF
10pF
1M
22μF
X5R
V
OUT
5V
450mA
3458 TA03a
V
IN
GND/PGND
SHDN
SYNC
R
T
I
LIM
SW
V
OUT
FB
COMP
SS
BURST
LTC3458
2 ALKALINE
1.8V to 3.3V
2.2μF
WURTH
12μH
774775112
ON OFF
243k 124k 133k
324k
33k
0.01μF
0.01μF
560pF
10pF
1M
22μF
X5R
V
OUT
5V
200mA
3458 TA04a
10pF
V
IN
GND/PGND
SHDN
SYNC
R
T
I
LIM
SW
V
OUT
FB
COMP
SS
BURST
LTC3458
Li-Ion
2.5V to 4.2V
2.2μF
COEV
10μH
DQ7545
ON OFF
200k 124k 133k
316k
33k
0.01μF
0.01μF
560pF
10pF
1.5M
22μF
X5R
V
OUT
7V
250mA
3458 TA05a
10pF
Lithium-Ion to 5V, 500mA at 850kHz
Two Cell to 5V
OUT
, 200mA at 850kHz
Lithium-Ion Battery to 7V
OUT
, 250mA at 1MHz
LOAD CURRENT (mA)
EFFICIENCY
100
95
90
85
80
75
70
65
0.1 10 100 1000
3458 TA03b
1
4.2V
IN
3.6V
IN
2.5V
IN
LOAD CURRENT (mA)
EFFICIENCY
100
95
90
85
80
75
70
65
0.1 10 100 1000
3458 TA04b
1
3.3V
IN
1.8V
IN
LOAD CURRENT (mA)
EFFICIENCY
100
95
90
85
80
75
70
65
0.1 10 100 1000
3458 TA05b
1
4.2V
IN
3.6V
IN
2.5V
IN
Li-Ion to 5V
OUT
Two Alkaline to 5V
OUT
Li-Ion to 7V
OUT
LTC3458
15
3458fa
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
PACKAGE DESCRIPTIO
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
4.00 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.50 REF
16
127
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0806 REV D
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE OUTLINE
3.30 ±0.10
0.25 ± 0.05
0.50 BSC
1.70 ± 0.05
3.30 ±0.05
0.50 BSC
0.25 ± 0.05

LTC3458EDE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.4A, 1.5MHz Sync Boost DC/DC Conv w/ Ou
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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