MAX8523
High-Speed, Dual-Phase Gate Driver for
Multiphase, Step-Down Converters
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Detailed Description
The MAX8523 dual-phase gate driver, along with the
MAX8524/MAX8525 multiphase controllers, provides
flexible 2- to 8-phase CPU core-voltage supplies. The
0.5Ω/0.95Ω driver resistance allows up to 30A output
current per phase.
Each MOSFET driver in the MAX8523 is capable of dri-
ving 3000pF capacitive loads with only 15ns propagation
delay and 11ns typical rise and fall times, allowing opera-
tions up to 1.2MHz per phase. Adaptive dead time con-
trols low-side MOSFET turn-on, and user-programmable
dead time controls high-side MOSFET turn-on. This maxi-
mizes converter efficiency, while allowing operation with a
variety of MOSFETs and PWM controller ICs. A UVLO cir-
cuit allows proper power-on sequencing. PWM_ signal
inputs are both TTL and CMOS compatible.
Principle of Operation
MOSFET Gate Drivers (DH_, DL_)
The high-side drivers (DH_) have typical 0.8Ω sourcing
resistance and 0.65Ω sinking resistance, resulting in 6A
peak sourcing current and 7A peak sinking current with
5V supply voltage. The low-side drivers (DL_) have typ-
ical 0.95Ω sourcing resistance and 0.5Ω sinking resis-
tance, yielding 5A peak sourcing current and 10A peak
sinking current. This reduces switching losses, making
the MAX8523 ideal for both high-frequency and high-
output-current applications.
Shoot-Through Protection
Adaptive shoot-through protection is incorporated for
the switching transition after the high-side MOSFET is
turned off and before the low-side MOSFET is turned
on. The low-side driver is turned on only when the LX
voltage falls below 1.8V. Furthermore, the delay time
between the low-side MOSFET turn-off and high-side
MOSFET turn-on can be adjusted by selecting the
value of R2 (see the R
DLY
Selection section).
Pin Description
PIN NAME FUNCTION
1 BST1
Boost Flying Capacitor Connection, Phase 1. Connect a 0.22µF or higher ceramic capacitor between
BST1 and LX1.
2 DH1 High-Side Gate-Driver Output, Phase 1
3 LX1 Switching Node (Inductor) Connection, Phase 1
4 PV1
Gate-Drive Supply for DL1. Bypass to PGND1 with a 2.2µF or higher capacitor. Connect PV1 and PV2
together.
5 DL1 Low-Side Gate-Driver Output, Phase 1
6 PGND1
Power Ground for DL1. Connect PGND1 and PGND2 together. Internal analog ground is connected to
PGND1.
7V
CC
Supply Voltage. Bypass V
CC
to PGND1 with a 0.1µF (min) capacitor.
8 DLY
Connect a resistor from DLY to PGND1 to set dead time between DL_ falling and DH_ rising. Connect to
V
CC
for default 20ns delay.
9 PWM1 Phase 1 PWM Logic Input. DH1 is high when PWM1 is high; DL1 is high when PWM1 is low.
10 PWM2 Phase 2 PWM Logic Input. DH2 is high when PWM2 is high; DL2 is high when PWM2 is low.
11 PGND2 Power Ground for DL2
12 DL2 Low-Side Gate-Driver Output, Phase 2
13 PV2
Gate-Drive Supply for DL2. Bypass to PGND2 with a 2.2µF or higher capacitor. Connect PV1 and PV2
together.
14 LX2 Switching Node (Inductor) Connection, Phase 2
15 DH2 High-Side Gate-Driver Output, Phase 2
16 BST2
Boost Flying Capacitor Connection, Phase 2. Connect a 0.22µF or higher ceramic capacitor between
BST2 and LX2.
