MC100LVE310FNR2G

MC100LVE310
www.onsemi.com
4
Table 6. LVNECL DC CHARACTERISTICS (V
CC
= 5.0 V, V
EE
= 3.3 V (Note 1))
Symbol
Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 55 60 55 60 65 70 mA
V
OH
Output HIGH Voltage (Note 2) 1085 1005 880 1025 955 880 1025 955 880 mV
V
OL
Output LOW Voltage (Note 2) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mV
V
IH
Input HIGH Voltage
(Single-Ended)
1165 880 1165 880 1165 880 mV
V
IL
Input LOW Voltage
(Single-Ended)
1810 1475 1810 1475 1810 1475 mV
V
BB
Output Voltage Reference 1.38 1.26 1.38 1.26 1.38 1.26 V
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
1.5 0.4 1.5 0.4 1.5 0.4 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ± 0.3 V.
2. Outputs are terminated through a 50 W resistor to V
CC
2 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. V
IHCMR
is defined as the range within which the V
IH
level may vary, with the device
still meeting the propagation delay specification. The V
IL
level must be such that the peak to peak voltage is less than 1.0 V and greater than
or equal to V
PP
(min).
Table 7. AC CHARACTERISTICS (V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
= 3.3 V (Note 1))
Symbol
Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
f
max
Maximum Toggle Frequency
@ V
out
> 500 mV
pp
0.5 1.0 0.5 1.0 0.5 1.0 GHz
t
PLH
t
PHL
Propagation Delay to Output
IN (Differential Configuration) (Note 2)
IN (Single-Ended) (Note 3)
525
500
725
750
550
550
750
800
575
600
775
850
ps
t
skew
Within-Device Skew (Note 4)
Part-to-Part Skew (Differential Configuration)
75
250
50
200
50
200
ps
t
JITTER
Additive CLOCK Jitter (RMS) < 0.5 GHz 1.5 2.0 1.5 2.0 1.5 2.0 ps
V
PP
Input Swing (Note5) 500 1000 500 1000 500 1000 mV
t
r
/t
f
Output Rise/Fall Time (20%80%)
200 600 200 600 200 600 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. V
EE
can vary ± 0.3 V.
2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. V
PP
(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The V
PP
(min) is AC limited
for the LVE310 as a differential input as low as 50 mV will still produce full ECL levels at the output.
MC100LVE310
www.onsemi.com
5
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
Termination of ECL Logic Devices)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
2.0 V
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
MC100LVE310
www.onsemi.com
6
PACKAGE DIMENSIONS
28 LEAD PLLC
CASE 77602
ISSUE F
N
M
L
V
W
D
D
Y BRK
28 1
VIEW S
S
L-M
S
0.010 (0.250) N
S
T
S
L-M
M
0.007 (0.180) N
S
T
0.004 (0.100)
G1
G
J
C
Z
R
E
A
SEATING
PLANE
S
L-M
M
0.007 (0.180) N
S
T
T
B
S
L-M
S
0.010 (0.250) N
S
T
S
L-M
M
0.007 (0.180) N
S
T
U
S
L-M
M
0.007 (0.180) N
S
T
Z
G1X
VIEW DD
S
L-M
M
0.007 (0.180) N
S
T
K1
VIEW S
H
K
F
S
L-M
M
0.007 (0.180) N
S
T
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.485 0.495 12.32 12.57
B 0.485 0.495 12.32 12.57
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.021 0.33 0.53
G 0.050 BSC 1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 --- 0.51 ---
K 0.025 --- 0.64 ---
R 0.450 0.456 11.43 11.58
U 0.450 0.456 11.43 11.58
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y --- 0.020 --- 0.50
Z 2 10 2 10
G1 0.410 0.430 10.42 10.92
K1 0.040 --- 1.02 ---
__ __

MC100LVE310FNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution 3.3V ECL 2:8 Diff Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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