PRODUCT SPECIFICATION ML4821
REV. 1.0.2 6/19/01 7
Figure 3. Error and Current Amplifier Configuration
Figure 4. Error Amplifier Open-loop Gain and
Phase vs. Frequency.
6
7
9
+
S.S
INV
+8V
V
REF
+8V
6.2k
EA OUT
V
CC
= 15V
V
O
= 1.0V TO 5.0V
R
L
= 100k
T
A
= 25°C
GAIN
PHASE
100
80
60
40
20
0
20
10 100 1.0k 10k 100k 1.0M 10M
0
30
60
90
120
150
180
f, FREQUENCY (Hz)
A
VOL
, OPEN-LOOP VOLTAGE GAIN (dB)
PHASE (DEGREES)
Figure 5. Output Saturation Voltage vs. Output Current. Figure 6. K-factor. Gain Modulator gain with respect to
the voltage at V
RMS
.
SOURCE
SATURATION
V
CC
T
A
= 25°C
T
A
= 55°C
T
A
= 55°C
T
A
= 25°C
V
CC
= 15V
80µs PULSED
LOAD
SINK
SATURATION
GND
0
.0
2
.0
3
.0
2
.0
.0
0
0 200 400 600 800
I
O
, OUTPUT LOAD CURRENT (mA)
0.5
0.4
0.3
0.2
0.1
0
1357460
85VAC
0.23
DESIGN
FOR
NORMAL
OPERATIONS
THIS IS THE MINIMUM
OPERATING
VOLTAGE POINT
THIS GAIN CURVE TAKES
OUT THE 1/(V
IN
)
2
DEPENDENCY OF THE
VOLTAGE CONTROL LOOP
120VAC
OPERATING BOUNDRY
220VAC
K
2
V
RMS
DESIGN
FOR
BROWNOUT
The output of the gain modulator is a current which appears
on IA+ to form the reference for the current error amplifier
and is given as:
I
GM
= K × I
SINE
× (V
EA
0.8)
where:
I
SINE
is the current in the dropping resistor, V
EA
is the
output of the error amplifier and K is a constant deter-
mined by the V
RMS
input.
The output current of the gain modulator is limited to:
This sets the system current limit.The multiplier output
current is converted into the reference voltage for the current
(IA) amplifier through a resistor to ground on IA+.
Figure 6 shows the gain adjustor (K) with respect to the
voltage at V
RMS
. The curve has been separated in two parts.
The right hand part is for operation under normal conditions
in the voltage range from minimum line voltage to maximum
line voltage (90VAC to 260VAC). 85VAC on the curve has
been chosen to account for tolerances. Under normal operat-
ing conditions as input voltage decreases the gain increases
compensating for the drop in the loop gain.
Under brownout conditions (below 85VAC) the gain
decreases to limit the amount of current that is drawn from
the line thus preventing an overload condition. This is a very
useful feature since in many cases the load for a PFC is a
constant power load. The input current has to go high to
compensate for a drop in the input voltage.
I
GM MAX()
2.5
R
T
--------=
ML4821 PRODUCT SPECIFICATION
8 REV. 1.0.2 6/19/01
Under Voltage Lockout, OVP and Current Limit
On power-up the ML4821 remains in the UVLO condition;
output low and quiescent current low. The IC becomes
operational when V
CC
reaches 16V. When V
CC
drops below
9V, the UVLO condition is imposed. During the UVLO
condition, the V
REF
pin is “off”, making it usable as a “flag”
for starting up a down-stream PWM converter.
OVP, Shutdown, and IC Bias
When the input to the OVP comparator exceeds V
REF
, the
output of the ML4821 is inhibited. The OVP input also
functions as a “sleep” input, putting the IC into the low
quiescent UVLO state when the OVP pin is pulled below
0.7V.
Figure 7. Gain Modulator Linearity. Figure 8. Under-Voltage Lockout Block Diagram.
500
0
0 100 300 400 500
SINE INPUT CURRENT (µA)
MULTIPLIER OUTPUT CURRENT (µA)
200
100
200
300
400
1.0
1.5
2.5
3.5
4.5
5.5
E/A OUTPUT VOLTAGE
R
T
= 5k
V
RMS
= 3V
ENABLE
V
REF
+
+
15
16
INTERNAL
BIAS
4.4V
LOGIC
POWER
V
REF
9V
V
CC
Figure 9. Total Supply Current vs. Supply Voltage.
Figure 10. Reference Load Regulation.
40
10
0
0102030
V
CC
SUPPLY VOLTAGE (V)
I
CC
SUPPLY CURRENT (mA)
T
A
= 25°C
20
30
V
CC
= 15V
T
A
= 55°C
T
A
= 25°C
T
A
= 125°C
0
4.0
8.0
12
16
20
24
0 20 40 60 80 100 120
I
REF
, REFERENCE SOURCE CURRENT (mA)
V
REF
, REFERENCE VOLTAGE CHANGE (mV)
PRODUCT SPECIFICATION ML4821
REV. 1.0.2 6/19/01 9
Off-line Start-up and Bias Supply Generation
The circuit in Figure 11 supplies V
CC
power to the ML4821.
Start-up current is delivered via R10. The IC starts when
V
CC
reaches 15.5V. After that time running power is
delivered through the tap on L1. The configuration shown
delivers a voltage proportional to the PFC output bus
voltage.
Figure 11. Bias and Start-up Circuit.
1000µF
R10
39k
2W
N
P
L1
TO IC
PIN 15
TO B+
N
S
N
P
N
S
V
OUT
14V
1µF
1µF

ML4821CS

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Power Factor Correction - PFC PFC Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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