MC34163, MC33163
http://onsemi.com
8
INTRODUCTION
The MC34163 series are monolithic power switching
regulators optimized for dc−to−dc converter applications.
The combination of features in this series enables the system
designer to directly implement step−up, step−down, and
voltage−inverting converters with a minimum number of
external components. Potential applications include cost
sensitive consumer products as well as equipment for the
automotive, computer, and industrial markets. A
Representative Block Diagram is shown in Figure 19.
OPERATING DESCRIPTION
The MC34163 operates as a fixed on−time, variable
off−time voltage mode ripple regulator. In general, this
mode of operation is somewhat analogous to a capacitor
charge pump and does not require dominant pole loop
compensation for converter stability. The Typical Operating
Waveforms are shown in Figure 20. The output voltage
waveform shown is for a step−down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
controlled by the oscillator, thus pumping up the output filter
capacitor. When the output voltage level reaches nominal,
the feedback comparator sets the latch, immediately
terminating switch conduction. The feedback comparator
will inhibit the switch until the load current causes the output
voltage to fall below nominal. Under these conditions,
output switch conduction can be inhibited for a partial
oscillator cycle, a partial cycle plus a complete cycle,
multiple cycles, or a partial cycle plus multiple cycles.
Oscillator
The oscillator frequency and on−time of the output switch
are programmed by the value selected for timing capacitor
C
T
. Capacitor C
T
is charged and discharged by a 9 to 1 ratio
internal current source and sink, generating a negative going
sawtooth waveform at Pin 6. As C
T
charges, an internal
pulse is generated at the oscillator output. This pulse is
connected to the NOR gate center input, preventing output
switch conduction, and to the AND gate upper input,
allowing the latch to be reset if the comparator output is low.
Thus, the output switch is always disabled during ramp−up
and can be enabled by the comparator output only at the start
of ramp−down. The oscillator peak and valley thresholds are
1.25 V and 0.55 V, respectively, with a charge current of
225 mA and a discharge current of 25 mA, yielding a
maximum on−time duty cycle of 90%. A reduction of the
maximum duty cycle may be required for specific converter
configurations. This can be accomplished with the addition
of an external deadtime resistor (R
DT
) placed across C
T
. The
resistor increases the discharge current which reduces the
on−time of the output switch. A graph of the Output Switch
On−Off Time versus Oscillator Timing Capacitance for
various values of R
DT
is shown in Figure 2. Note that the
maximum output duty cycle, t
on
/t
on
+ t
off
, remains constant
for values of C
T
greater than 0.2 nF. The converter output
can be inhibited by clamping C
T
to ground with an external
NPN small−signal transistor.
Feedback and Low Voltage Indicator Comparators
Output voltage control is established by the Feedback
comparator. The inverting input is internally biased at 1.25 V
and is not pinned out. The converter output voltage is
typically divided down with two external resistors and
monitored by the high impedance noninverting input at Pin 2.
The maximum input bias current is ±0.4 mA, which can cause
an output voltage error that is equal to the product of the input
bias current and the upper divider resistance value. For
applications that require 5.0 V, the converter output can be
directly connected to the noninverting input at Pin 3. The high
impedance input, Pin 2, must be grounded to prevent noise
pickup. The internal resistor divider is set for a nominal
voltage of 5.05 V. The additional 50 mV compensates for a
1.0% voltage drop in the cable and connector from the
converter output to the load. The Feedback comparator’s
output state is controlled by the highest voltage applied to
either of the two noninverting inputs.
The Low Voltage Indicator (LVI) comparator is designed
for use as a reset controller in microprocessor−based
systems. The inverting input is internally biased at 1.125 V,
which sets the noninverting input thresholds to 90% of
nominal. The LVI comparator has 15 mV of hysteresis to
prevent erratic reset operation. The Open Collector output is
capable of sinking in excess of 6.0 mA (see Figure 11). An
external resistor (R
LVI
) and capacitor (C
DLY
) can be used to
program a reset delay
time (t
DLY
) by the formula shown
below, where V
th(MPU)
is the microprocessor reset input
threshold. Refer to Figure 21.
Ǔǒ
t
DLY
= R
LVI
C
DLY
In
1
1 −
V
th(MPU)
V
out
Current Limit Comparator, Latch and Thermal
Shutdown
With a voltage mode ripple converter operating under
normal conditions, output switch conduction is initiated by
the oscillator and terminated by the Voltage Feedback
comparator. Abnormal operating conditions occur when the
converter output is overloaded or when feedback voltage
sensing is lost. Under these conditions, the Current Limit
comparator will protect the Output Switch.
