74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
March 2007
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC109, 74ACT109 Rev. 1.5
74AC109, 74ACT109
Dual JK
Positive Edge-Triggered Flip-Flop
Features
■
I
CC
reduced by 50%
■
Outputs source/sink 24mA
■
ACT109 has TTL-compatible inputs
General Description
The AC/ACT109 consists of two high-speed completely
independent transition clocked JK
flip-flops. The clocking
operation is independent of rise and fall times of the
clock waveform. The JK
design allows operation as a
D-Type flip-flop (refer to AC/ACT74 data sheet) by
connecting the J and K
inputs together.
Asynchronous Inputs:
– LOW input to S
D
(Set) sets Q to HIGH level
– LOW input to C
D
(Clear) sets Q to LOW level
– Clear and Set are independent of clock
– Simultaneous LOW on C
D
and S
D
makes both
Q and Q HIGH
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram Pin Descriptions
Order
Number
Package
Number Package Description
74AC109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
J
1
, J
2
, K
1
, K
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
, C
D2
Direct Clear Inputs
S
D1
, S
D2
Direct Set Inputs
Q
1
, Q
2
, Q
1
, Q
2
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation
.