4©2017 Integrated Device Technology, Inc. September 22, 2017
8S89832I Data Sheet
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
Surge Current
10mA
15mA
Input Current, IN, nIN ±50mA
V
T
Current, I
VT
±100mA
Input Sink/Source, I
REF_AC
± 0.5mA
Operating Temperature Range, T
A
-40°C to +85°C
Package Thermal Impedance,
JA
, (Junction-to-Ambient) 74.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 95 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 1.7 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.7 V
I
IH
Input High Current V
DD
= V
IN
= 2.625V 10 µA
I
IL
Input Low Current V
DD
= 2.625V, V
IN
= 0V -150 µA
5©2017 Integrated Device Technology, Inc. September 22, 2017
8S89832I Data Sheet
Table 4C. Differential DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Guaranteed by design.
Table 4D. LVDS DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
AC Electrical Characteristics
Table 5. AC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
All parameters are measured at 1.5GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
R
IN
Differential Input Resistance IN, nIN IN to VT, nIN to VT 40 50 60
V
IH
Input High Voltage IN, nIN 1.2 V
DD
V
V
IL
Input Low Voltage IN, nIN 0 V
IH
– 0.15 V
V
IN
Input Voltage Swing; NOTE 1 0.15 1.2 V
V
DIFF_IN
Differential Input Voltage Swing 0.3 V
I
IN
Input Current; NOTE 2 IN, nIN 35 mA
V
REF_AC
Reference Voltage V
DD
– 1.40 V
DD
– 1.35 V
DD
– 1.30 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 247 454 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 1.125 1.375 V
V
OS
V
OS
Magnitude Change 50 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Operating Frequency 2GHz
t
PD
Propagation Delay; (Differential)
NOTE 1
300 550 ps
tsk(o) Output Skew; NOTE 2, 3 25 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 200 ps
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
200MHz, Integration Range:
12kHz - 20MHz
0.09 ps
t
s
/t
H
Clock Enable Setup Time EN to IN, nIN 300 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 50 235 ps
6©2017 Integrated Device Technology, Inc. September 22, 2017
8S89832I Data Sheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a Phase
noise plot and is most often the specified plot in many applications.
Phase noise is defined as the ratio of the noise power present in a
1Hz band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency
domain, we get a better understanding of its effects on the desired
application over the entire time record of the signal. It is
mathematically possible to calculate an expected bit error rate given
a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator”.
Additive Phase Jitter @ 200MHz
12kHz to 20MHz = 0.09ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)

8S89832AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Skew,1-to-4 LVDS Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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