6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges
13
Waveform of Write Cycle No.1 (R/W Controlled Timing)
Random Access Port
(1,6)
Waveform of Write Cycle No.2 (CE, LB, and/or UB Controlled Timing)
Random Access Port
(1,6,7)
NOTES:
1. R/W, CE, or LB and UB must be inactive during all address transitions.
2. A write occurs during the overlap of R/W = V
IL, CE = VIL and LB = VIL and/or UB = VIL.
3. t
WR is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and the input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. OE is continuously HIGH, OE = V
IH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to
turn off and on the data to be placed on the bus for the required t
DW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum
write pulse is the specified t
WP. For the CE controlled write cycle, OE may be LOW with no degregation to tCW timing.
7. I/O
OUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. CMD access follows the standard CE access described above. If CMD = V
IL, then CE must = VIH or, when CE = VIL, CMD must = VIH.
CE, LB, UB
ADDR
t
AW
t
WR
t
DW
I/O
IN
t
WC
t
WP
t
DH
R/W
t
AS
I/O
OUT
t
WHZ
t
BE
t
ACS
OE
t
OHZ
t
OW
3099 drw 15
(5)
(2)
(3)
Data Out
Data Out
(4)
(4)
Valid Data In
(8)
t
WR
E, LB, UB
t
AW
t
DW
I/O
IN
ADDR
WC
R/W
t
DH
t
AS
3099 drw 16
Valid Data
(5)
t
BP
(2)
t
CW
(2)
(3)
(8)
