AD7810YRZ-REEL7 Datasheet AD7810YRZ, AD7810YRZ-REEL7, AD7810YRZ-REEL | P7-P9

AD7810

–6–

REV. B

CIRCUIT DESCRIPTION

Converter Operation

The AD7810 is a successive approximation analog-to-digital

converter based around a charge redistribution DAC. The ADC

can convert analog input signals in the range 0 V to V

. Fig-

ures 4 and 5 below show simplified schematics of the ADC.

Figure 4 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in Position A; the comparator is held in a

balanced condition; and the sampling capacitor acquires the

signal on V

IN+

CHARGE

REDISTRIBUTION

DAC

COMPARATOR

CONTROL

LOGIC

CLOCK

OSC

SAMPLING

CAPACITOR

ACQUISITION

PHASE

SW2

SW1

–

Figure 4. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 5), SW2 will

open and SW1 will move to Position B, causing the comparator

to become unbalanced. The control logic and the charge redis-

tribution DAC are used to add and subtract fixed amounts of

charge from the sampling capacitor to bring the comparator

back into a balanced condition. When the comparator is rebal-

anced, the conversion is complete. The control logic generates

the ADC output code. Figure 11 shows the ADC transfer function.

CHARGE

REDISTRIBUTION

DAC

COMPARATOR

CONTROL

LOGIC

CLOCK

OSC

SAMPLING

CAPACITOR

CONVERSION

PHASE

SW2

SW1

–

Figure 5. ADC Conversion Phase

TYPICAL CONNECTION DIAGRAM

Figure 6 shows a typical connection diagram for the AD7810. The

serial interface is implemented using two wires; the rising edge

of CONVST enables the serial interface—see Serial Interface

section for more details. V

REF

is connected to a well decoupled

pin to provide an analog input range of 0 V to V

. When

is first connected, the AD7810 powers up in a low current

mode, i.e., power-down. A rising edge on the CONVST input

will cause the part to power up—see Operating Modes. If power

consumption is of concern, the automatic power-down at the

end of a conversion should be used to improve power perfor-

mance. See Power vs. Throughput Rate section of the data sheet.

OUT

SCLK

REF

AGND

–

CONVST

SUPPLY

2.7V TO 5.5V

0V TO V

REF

INPUT

AD7810

0.1␮F10␮F

TWO WIRE

SERIAL

INTERFACE

␮C/␮P

Figure 6. Typical Connection Diagram

Analog Input

Figure 7 shows an equivalent circuit of the analog input struc-

ture of the AD7810. The two diodes, D1 and D2, provide ESD

protection for the analog inputs. Care must be taken to ensure

that the analog input signal never exceeds the supply rails by

more than 200 mV. This will cause these diodes to become

forward biased and start conducting current into the substrate.

The maximum current these diodes can conduct without caus-

ing irreversible damage to the part is 20 mA. The capacitor C2

is typically about 4 pF and can be primarily attributed to pin

capacitance. The resistor R1 is a lumped component made up of

the on resistance of a multiplexer and a switch. This resistor is

typically about 125 Ω. The capacitor C1 is the ADC sampling

capacitor and has a capacitance of 3.5 pF.

3.5pF

125⍀

4pF

CONVERT PHASE – SWITCH OPEN

ACQUISITION PHASE – SWITCH CLOSED

Figure 7. Equivalent Analog Input Circuit

The analog input of the AD7810 is made up of a pseudo differ-

ential pair. V

IN+

pseudo differential with respect to V

IN–

. The

signal is applied to V

IN+

, but in the pseudo differential scheme

the sampling capacitor is connected to V

IN–

during conversion

(see Figure 8). This input scheme can be used to remove offsets

that exist in a system. For example, if a system had an offset of

0.5 V, the offset could be applied to V

IN–

and the signal applied

to V

IN+

. This has the effect of offsetting the input span by 0.5 V.

It is only possible to offset the input span when the reference

voltage (V

REF

) is less than V

– V

OFFSET

COMPARATOR

CONTROL

LOGIC

CLOCK

OSC

SAMPLING

CAPACITOR

CONVERSION

PHASE

SW2

–

CHARGE

REDISTRIBUTION

DAC

OFFSET

(+)

OFFSET

Figure 8. Pseudo Differential Input Scheme

AD7810

–7–

REV. B

When using the pseudo differential input scheme, the signal on

IN–

must not vary by more than a 1/2 LSB during the conver-

sion process. If the signal on V

IN–

varies during conversion, the

conversion result will be incorrect. For single-ended operation,

IN–

is always connected to AGND. Figure 9 shows the AD7810

pseudo differential input being used to make a unipolar dc cur-

rent measurement. A sense resistor is used to convert the current

to a voltage and the voltage, is applied to the differential input

as shown.

SENSE

–

AD7810

Figure 9. DC Current Measurement Scheme

DC Acquisition Time

The ADC starts a new acquisition phase at the end of a conver-

sion and ends on the falling edge of the CONVST signal. At the

end of a conversion there is a settling time associated with the

sampling circuit. This settling time lasts approximately 100 ns.

The analog signal on V

IN+

is also being acquired during this

settling time; therefore, the minimum acquisition time needed is

approximately 100 ns.

Figure 10 shows the equivalent charging circuit for the sampling

capacitor when the ADC is in its acquisition phase. R2 repre-

sents the source impedance of a buffer amplifier or resistive

network; R1 is an internal multiplexer resistance and C1 is the

sampling capacitor.

3.5pF

125⍀

Figure 10. Equivalent Sampling Circuit

During the acquisition phase, the sampling capacitor must be

charged to within a 1/2 LSB of its final value. The time it takes

to charge the sampling capacitor (t

CHARGE

) is given by the fol-

lowing formula:

CHARGE

= 7.6 × (R2 + 125 Ω) × 3.5 pF

For small values of source impedance, the settling time associated

with the sampling circuit (100 ns) is, in effect, the acquisition

time of the ADC. For example, with a source impedance (R2)

of 10 Ω, the charge time for the sampling capacitor is approxi-

mately 4 ns. The charge time becomes significant for source

impedances of 2 kΩ and greater.

AC Acquisition Time

In ac applications it is recommended to always buffer analog

input signals. The source impedance of the drive circuitry must

be kept as low as possible to minimize the acquisition time of

the ADC. Large values of source impedance will cause the THD

to degrade at high throughput rates. In addition, better perfor-

mance can generally be achieved by using an external 1 nF

capacitor on V

IN+

ADC TRANSFER FUNCTION

The output coding of the AD7810 is straight binary. The

designed code transitions occur at successive integer LSB values

(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V

REF

/1024. The

ideal transfer characteristic for the AD7810 is shown in Figure

11 below.

000...010

000...001

000...000

ADC CODE

0V +V

REF

–1LSB

ANALOG INPUT

111...111

111...110

111...000

011...111

1LSB

1LSB = V

REF

/1024

Figure 11. Transfer Characteristic

AD7810

–8–

REV. B

POWER-UP TIMES

The AD7810 has a 1.5 µs power-up time. When V

is first

connected, the AD7810 is in a low current mode of operation.

In order to carry out a conversion, the AD7810 must first be

powered up. The ADC is powered up by a rising edge on the

CONVST pin. A conversion is initiated on the falling edge of

CONVST. Figure 12 shows how to power up the AD7810 when

is first connected or after the AD7810 is powered down

using the CONVST pin.

Care must be taken to ensure that the CONVST pin of the

AD7810 is logic low when V

is first applied.

MODE 1 (CONVST IDLES HIGH)

MODE 2 (CONVST IDLES LOW)

< 1␮s

POWER-UP

1.5␮s

POWER-UP

1.5␮s

CONVST

Figure 12. Power-Up Times

POWER VS. THROUGHPUT RATE

By operating the AD7810 in Mode 2, the average power con-

sumption of the AD7810 decreases at lower throughput rates.

Figure 13 shows how the automatic power-down is implemented

using the CONVST signal to achieve the optimum power per-

formance for the AD7810. As the throughput rate is reduced, the

device remains in its power-down state longer and the average

power consumption over time drops accordingly.

CYCLE

100␮s @ 10kSPS

CONVST

CONVERT

2.3␮s

POWER-DOWN

POWER-UP

1.5␮s

Figure 13. Automatic Power-Down

For example, if the AD7810 is operated in a continuous sampling

mode with a throughput rate of 10 kSPS, the power consump-

tion is calculated as follows. The power dissipation during normal

operation is 9 mW, V

= 3 V. If the power-up time is 1.5 µs

and the conversion time is 2.3 µs, the AD7810 can be said to

dissipate 9 mW for 3.8 µs (worst case) during each conversion

cycle. If the throughput rate is 10 kSPS, the cycle time is

100 µs and the average power dissipated during each cycle is

(3.8/100) × (9 mW) = 342 µW. Figure 2 shows a graph of

Power vs. Throughput.

OPERATING MODES

Mode 1 Operation (High Speed Sampling)

When the AD7810 is used in this mode of operation, the part is

not powered down between conversions. This mode of opera-

tion allows high throughput rates to be achieved. The timing

diagram in Figure 14 shows how this optimum throughput rate

is achieved by bringing the CONVST signal high before the end

of the conversion. The AD7810 leaves its tracking mode and

goes into hold on the falling edge of CONVST. A conversion is

also initiated at this time. The conversion takes 2.3 µs to complete.

At this point, the result of the current conversion is latched into the

serial shift register, and the state of the CONVST signal checked.

The CONVST signal should be high at the end of the conversion

to prevent the part from powering down.

OUT

CURRENT CONVERSION RESULT

SCLK

CONVST

Figure 14. Mode 1 Operation Timing

The serial port on the AD7810 is enabled on the rising edge of

the CONVST signal (see Serial Interface section). As explained

earlier, this rising edge should occur before the end of the con-

version process if the part is not to be powered down. A serial

read can take place at any stage after the rising edge of CONVST.

If a serial read is initiated before the end of the current con-

version process (i.e., at time “A”), the result of the previous

conversion is shifted out on the D

OUT

pin. It is possible to allow

the serial read to extend beyond the end of a conversion. In this

case the new data will not be latched into the output shift regis-

ter until the read has finished. The dynamic performance of the

AD7810 typically degrades by up to 3 dBs while reading during

a conversion. If the user waits until the end of the conversion

process, i.e., 2.3 µs after falling edge of CONVST (Point “B”),

before initiating a read, the current conversion result is shifted out.

P1-P3 P4-P6 P7-P9 P10-P12

AD7810YRZ-REEL7

Mfr. #:

Buy AD7810YRZ-REEL7

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 2.7V-5.5V 2ms 10-Bit

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AD7810YRZ-REEL7

AD7810YRZ-REEL7

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