7
FN3072.7
October 10, 2005
The voltage regulator portion of the ICL7660 and ICL7660A is
an integral part of the anti-latchup circuitry, however its inherent
voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the “LV” pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 3.5V the LV terminal must be left open to
insure latchup proof operation, and prevent device damage.
Theoretical Power Efficiency
Considerations
In theory a voltage converter can approach 100% efficiency
if certain conditions are met.
1. The driver circuitry consumes minimal power.
2. The output switches have extremely low ON resistance
and virtually no offset.
3. The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.
The ICL7660 and ICL7660A approach these conditions for
negative voltage conversion if large values of C
1
and C
2
are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E =
1
/
2
C
1
(V
1
2
- V
2
2
)
where V
1
and V
2
are the voltages on C
1
during the pump and
transfer cycles. If the impedances of C
1
and C
2
are relatively
high at the pump frequency (refer to Figure 12) compared to
the value of R
L
, there will be a substantial difference in the
voltages V
1
and V
2
. Therefore it is not only desirable to make
C
2
as large as possible to eliminate output voltage ripple, but
also to employ a correspondingly large value for C
1
in order to
achieve maximum efficiency of operation.
Do’s And Don’ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GROUND for supply
voltages greater than 3.5V.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay.
4. When using polarized capacitors, the + terminal of C
1
must be connected to pin 2 of the ICL7660 and ICL7660A
and the + terminal of C
2
must be connected to GROUND.
5. If the voltage supply driving the ICL7660 and ICL7660A
has a large source impedance (25 - 30), then a 2.2µF
capacitor from pin 8 to ground may be required to limit
rate of rise of input voltage to less than 2V/µs.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions. A 1N914 or similar diode placed
in parallel with C
2
will prevent the device from latching up
under these conditions. (Anode pin 5, Cathode pin 3).
V
OUT
= -V
IN
C
2
V
IN
C
1
S
3
S
4
S
1
S
2
8
3
2
5
3
7
FIGURE 12. IDEALIZED NEGATIVE VOLTAGE CONVERTER
FIGURE 13A. CONFIGURATION FIGURE 13B. THEVENIN EQUIVALENT
FIGURE 13. SIMPLE NEGATIVE CONVERTER
1
2
3
4
8
7
6
5
+
-
10µF
ICL7660
V
OUT
= -V+
V+
+
-
10µF
ICL7660A
V+
+
-
R
O
V
OUT
ICL7660, ICL7660A
8
FN3072.7
October 10, 2005
Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the ICL7660
and ICL7660A for generation of negative supply voltages.
Figure 13 shows typical connections to provide a negative
supply negative (GND) for supply voltages below 3.5V.
The output characteristics of the circuit in Figure 13A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 13B. The voltage source has
a value of -V+. The output impedance (R
O
) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 12), the switching frequency, the value of C
1
and C
2
,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for R
O
is:
RSW, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance
graphs), typically 23 at 25°C and 5V. Careful selection of
C
1
and C
2
will reduce the remaining terms, minimizing the
output impedance. High value capacitors will reduce the
1/(f
PUMP
C
1
) component, and low ESR capacitors will
lower the ESR term. Increasing the oscillator frequency will
reduce the 1/(f
PUMP
C1) term, but may have the side effect
of a net increase in output impedance when C
1
> 10µF and
there is no longer enough time to fully charge the capacitors
FIGURE 14. OUTPUT RIPPLE
FIGURE 15. PARALLELING DEVICES
FIGURE 16. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
A
t
2
t
1
B
0
-(V+)
V
1
2
3
4
8
7
6
5
ICL7660
V+
C
1
ICL7660A
1
2
3
4
8
7
6
5
ICL7660
C
1
ICL7660A
R
L
+
-
C
2
“n”
“1”
1
2
3
4
8
7
6
5
V+
1
2
3
4
8
7
6
5
+
-
10µF
+
-
10µF
+
-
10µF
+
-
10µF
V
OUT
= -nV+
ICL7660
ICL7660A
“n”
ICL7660
ICL7660A
“1”
R
O
2(R
SW1
+ R
SW3
+ ESR
C1
) +
2(R
SW2
+ R
SW4
+ ESR
C1
) +
1
+ ESR
C2
(f
PUMP
) (C1)
(f
PUMP
=
f
OSC
, R
SWX
= MOSFET switch resistance)
2
Combining the four R
SWX
terms as R
SW
, we see that:
R
O
2 (R
SW
) +
1
+ 4 (ESR
C1
) + ESR
C2
(f
PUMP
) (C1)
R
O
2(R
SW1
+ R
SW3
+ ESR
C1
) +
ICL7660, ICL7660A
9
FN3072.7
October 10, 2005
every cycle. In a typical application where f
OSC
= 10kHz and
C = C
1
= C
2
= 10µF:
R
O
46 + 20 + 5 (ESR
C
)
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f
PUMP
C
1
) term, rendering an
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.
R
O/
46 + 20 + 5 (ESR
C
)
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f
PUMP
C
1
) term, rendering an
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 14. Segment A is the voltage drop across the ESR of
C
2
at the instant it goes from being charged by C
1
(current
flow into C
2
) to being discharged through the load (current
flowing out of C
2
). The magnitude of this current change is
2 I
OUT
, hence the total drop is 2 I
OUT
eSR
C2
V. Segment
B is the voltage change across C
2
during time t
2
, the half of
the cycle when C
2
supplies current to the load. The drop at B
is l
OUT
t2/C
2
V. The peak-to-peak ripple voltage is the sum
of these voltage drops:
Again, a low ESR capacitor will reset in a higher
performance output.
Paralleling Devices
Any number of ICL7660 and ICL7660A voltage converters
may be paralleled to reduce output resistance. The reservoir
capacitor, C
2
, serves all devices while each device requires
its own pump capacitor, C
1
. The resultant output resistance
would be approximately:
Cascading Devices
The ICL7660 and ICL7660A may be cascaded as shown to
produced larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
V
OUT
= -n (V
IN
),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660
and ICL7660A R
OUT
values.
Changing the ICL7660/ICL7660A Oscillator
Frequency
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an
external clock, as shown in Figure 17. In order to prevent
possible device latchup, a 1k resistor must be used in
series with the clock output. In a situation where the
designer has generated the external clock frequency using
TTL logic, the addition of a 10k pullup resistor to V+ supply
is required. Note that the pump frequency with external
clocking, as with internal clocking, will be
1
/
2
of the clock
frequency. Output transitions occur on the positive-going
edge of the clock.
It is also possible to increase the conversion efficiency of the
ICL7660 and ICL7660A at low load levels by lowering the
oscillator frequency. This reduces the switching losses, and is
shown in Figure 18. However, lowering the oscillator
frequency will cause an undesirable increase in the
impedance of the pump (C
1
) and reservoir (C
2
) capacitors;
this is overcome by increasing the values of C
1
and C
2
by the
same factor that the frequency has been reduced. For
example, the addition of a 100pF capacitor between pin 7
(OSC) and V+ will lower the oscillator frequency to 1kHz from
its nominal frequency of 10kHz (a multiple of 10), and thereby
necessitate a corresponding increase in the value of C
1
and
C
2
(from 10µF to 100µF).
R
O
2 (23) +
1
+ 4 (ESR
C1
) + ESR
C2
(5 10
3
) (10
-5
)
R
O
2 (23) +
1
+ 4 (ESR
C1
) + ESR
C2
(5 10
3
) (10-
5
)
V
RIPPLE
[
1
+ 2 (ESR
C2
)
]
I
OUT
2 (f
PUMP
) (C2)
R
OUT
=
R
OUT
(of ICL7660/ICL7660A)
n (number of devices)
1
2
3
4
8
7
6
5
+
-
10µF
ICL7660
V
OUT
V+
+
-
10µF
V+
CMOS
GATE
1k
ICL7660A
FIGURE 17. EXTERNAL CLOCKING
ICL7660, ICL7660A

ICL7660CPAZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Voltage Regulators W/ANNEAL CMOS VOLT CONVRTR 8 PDIP COM
Lifecycle:
New from this manufacturer.
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