LTC1069-6
6
10696fa
PIN FUNCTIONS
for single supply operation, the internal biasing of Pin 1
allows optimum output swing. The AGND pin should be
buffered if used to bias other ICs. Figure 2 shows the
connections for single supply operation.
AGND
V
+
V
+
NC
V
IN
V
IN
V
OUT
V
OUT
V
–
1
2
3
4
8
7
6
5
1k
NC
CLK
LTC1069-6
ANALOG GROUND PLANE
DIGITAL
GROUND
PLANE
0.47μF
0.1μF
1069-6 F02
CLOCK
SOURCE
STAR
SYSTEM
GROUND
V
+
, V
–
(Pins 2, 7): Power Supply Pins. The V
+
(Pin 2)
and the V
–
(Pin 7, if used) should be bypassed with a
0.1μF capacitor to an adequate analog ground. The fi lter’s
power supplies should be isolated from other digital or
high voltage analog supplies. A low noise linear supply is
recommended. Switching power supplies will lower the
signal-to-noise ratio of the fi lter. Unlike previous monolithic
fi lters, the power supplies can be applied in any order, that
is, the positive supply can be applied before the negative
supply and vice versa. Figure 3 shows the connection for
dual supply operation.
AGND
V
+
V
+
NC
V
IN
V
IN
V
OUT
V
OUT
V
–
V
–
1
2
3
4
8
7
6
5
1k
NC
CLK
LTC1069-6
ANALOG GROUND PLANE
DIGITAL
GROUND
PLANE
STAR
SYSTEM
GROUND
0.1μF 0.1μF
1069-6 F03
CLOCK
SOURCE
Figure 2. Connections for Single Supply Operation
Figure 3. Connections for Dual Supply Operation
NC (Pins 3, 6): No Connection. Pins 3 and 6 are not
connected to any internal circuitry; they should be tied
to ground.
V
IN
(Pin 4): Filter Input Pin. The Filter Input pin is internally
connected to the inverting input of an op amp through a
50k resistor.
CLK (Pin 5): Clock Input Pin. Any TTL or CMOS clock
source with a square wave output and 50% duty cycle
(±10%) is an adequate clock source for the device. The
power supply for the clock source should not necessarily
be the fi lter’s power supply. The analog ground of the fi lter
should be connected to the clock’s ground at a single
point only. Table 1 shows the clock’s low and high level
threshold value for a dual or single supply operation. A
pulse generator can be used as a clock source provided
the high level ON time is greater than 0.42μs (V
S
= ±5V).
Sine waves less than 100kHz are not recommended for
clock frequencies because, excessive slow clock rise or
fall times generate internal clock jitter. The maximum clock
rise or fall time is 1μs. The clock signal should be routed
from the right side of the IC package to avoid coupling
into any input or output analog signal path. A 1k resistor
between the clock source and the Clock Input (Pin 5) will
slow down the rise and fall times of the clock to further
reduce charge coupling (Figure 1).
Table 1. Clock Source High and Low Thresholds
POWER SUPPLY HIGH LEVEL LOW LEVEL
Dual Supply = ±5V 1.5V 0.5V
Single Supply = 10V 6.5V 5.5V
Single Supply = 5V 1.5V 0.5V
Single Supply = 3.3V 1.2V 0.5V
V
OUT
(Pin 8): Filter Output Pin. Pin 8 is the output of the
fi lter, and it can source 8mA or sink 1mA. The total harmonic
distortion of the fi lter will degrade when driving coaxial
cables or loads less than 20k without an output buffer.
