LT1055/LT1056
10
10556fd
For more information www.linear.com/LT1055
APPLICATIONS INFORMATION
printed circuit board is required. Bulk leakage reduction
depends on the guard ring width.
The LT1055/LT1056 has the lowest offset voltage of any
JFET input op amp available today. However, the offset
voltage and its drift with time and temperature are still
not as good as on the best bipolar amplifiers because the
transconductance of FETs is considerably lower than that
of bipolar transistors. Conversely, this lower transcon-
ductance is the main cause of the significantly faster speed
performance of FET input op amps.
Offset voltage also changes somewhat with temperature
cycling. The AM grades show a typical 20µV hysteresis
(30µV on the M grades) when cycled over the –55°C to
125°C temperature range. Temperature cycling from 0°C
to 70°C has a negligible (less than 10µV) hysteresis effect.
The offset voltage and drift performance are also affected
by packaging. In the plastic N8 package the molding com
-
pound is in direct contact with the chip, exerting pressure
on the sur
face
. While NPN input transistors are largely
unaffected by this pressure, JFET device matching and drift
are degraded. Consequently, for best DC performance, as
shown in the typical performance distribution plots, the
TO-5 H package is recommended.
Noise Performance
The current noise of the LT1055/LT1056 is practically
immeasurable at 1.8fA/√Hz. At 25°C it is negligible up to
1G of source resistance, R
S
(compound to the noise of
R
S
). Even at 125°C it is negligible to 100M of R
S
.
The voltage noise spectrum is characterized by a low 1/f
corner in the 20Hz to 30Hz range, significantly lower than
on other competitive JFET input op amps. Of particular
interest is the fact that with any JFET IC amplifier, the
frequency location of the 1/f corner is proportional to
the square root of the internal gate leakage currents and,
therefore, noise doubles every 20°C. Furthermore, as il
-
lustrated in the noise versus chip temperature curves, the
0.1
Hz to
10Hz peak-to-peak noise is a strong function of
temperature, while wideband noise (f
O
= 1kHz) is practi-
cally unaffected by temperature.
Consequently,
for optimum low frequency noise, chip
temperature should be minimized. For example, operat
-
ing an LT1056 at ±5V supplies or with a 20°
C/
W case-
to-ambient heat sink reduces 0.1Hz to 10Hz noise from
typically 2.5µV
P-P
(±15V, free-air) to 1.5µV
P-P
. Similiarly,
the noise of an LT1055 will be 1.8µV
P-P
typically because
of its lower power dissipation and chip temperature.
High Speed Operation
Settling time is measured in the test circuit shown. This test
configuration has two features which eliminate problems
common to settling time measurments: (1) probe capaci
-
tance is isolated from the “false summing” node, and (2)
it does not require a “flat top” input pulse since the input
pulse is merely used to steer current through the diode
bridges. For more details, please see Application Note 10.
As with most high speed amplifiers, care should be taken with
supply decoupling, lead dress and component placement.
When the feedback around the op amp is resistive (R
F
),
a pole will be created with R
F
, the source resistance and
capacitance (R
S
, C
S
), and the amplifier input capacitance
(C
IN
≈ 4pF). In low closed-loop gain configurations and
with R
S
and R
F
in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capaci-
tor (
C
F
) in parallel with R
F
eliminates this problem. With
R
S
(C
S
+ C
IN
) = R
F
C
F
, the effect of the feedback pole is
completely removed.
–
+
R
S
R
F
F
C
S
C
IN
LT1055/56 AI03
Phase Reversal Protection
Most industry standard JFET input op amps (e.g., LF155/
LF156, LF351, LF411, OP15/16) exhibit phase reversal at
the output when the negative common mode limit at the
input is exceeded (i.e., from –12V to –15V with ±15V sup
-
plies). This can cause lock-up in servo systems. As shown
below
,
the LT1055/LT1056 does not have this problem
due to unique phase reversal protection circuitry (Q1 on
simplified schematic).
