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XC6121/XC6122/XC6123/XC6124
Series
■OPERATIONAL EXPLANATION
The XC6121/6122/6123/6124 series compare, using the error amplifier, the voltage of the internal voltage reference source
with the voltage divided by R1, R2 and R3 connected to the VIN pin. The resulting output signal from the error amplifier
activates the watchdog logic, delay circuit and the output driver. When the V
IN pin voltage gradually falls and finally reaches
the detect voltage, the RESETB pin output goes from high to low in the case of the VDFL type ICs.
<RESETB / RESET Pin Output Signal>
* V
DFL (RESETB) type - output signal: Low when detected.
The RESETB pin output goes from high to low whenever the VIN pin voltage falls below the detect voltage. The RESETB pin
remains low for the release delay time (t
DR) after the VIN pin voltage reaches the release voltage. If neither rising nor falling
signals are applied to the WD pin within the watchdog timeout period, the RESETB pin output remains low for the release
delay time (tDR), and thereafter the RESET pin outputs high level signal.
<Hysteresis>
When the internal comparator output is high, the NMOS transistor connected in parallel to R3 is turned ON, activating the
hysteresis circuit. The difference between the release and detect voltages represents the hysteresis width, as shown by the
following calculations:
V
DFL (detect voltage) = (R1+R2+R3) x Vref / (R2+R3)
V
DR (release voltage) = (R1+R2) x Vref / (R2)
VHYS (hysteresis width) =VDR-VDFL (V)
VDR > VDFL
* Please refer to the block diagrams for R1, R2, R3 and Vref.
* Hysteresis width is selectable from V
DFL x 0.05V (TYP.).
<Watchdog (WD) Pin>
The series use a watchdog timer to detect malfunction or “runaway” of the microprocessor. If neither rising nor falling signals
are applied from the microprocessor within the watchdog timeout period, the RESETB pin output maintains the detection state
for the release delay time (t
DR), and thereafter the RESETB pin outputs low to high signal. The watchdog pin is pulled down
to the V
SS
internally. When the watchdog pin is not connected, A reset signal comes out after the watchdog timeout period.
Six watchdog timeout period settings (tWD) are available in 1.6s, 800ms, 400ms, 200ms, 100ms, and 50ms.
<EN Pin>
In case where the watchdog function is not used, When the EN pin input driven to low level, only the watchdog function is
forced off while the detect voltage circuit remains operation. For using the watchdog function, the EN pin should be used in
high level. Even after the input voltage and the EN pin voltage are driven back high, the RESETB pin output maintains the
detection state for the release delay time (T
DR). (Refer to the TIMING CHART 1-①.) The watchdog function recovers
immediately when the input voltage becomes higher than the release voltage and the EN pin voltage driven from low to high
level. (Refer to the TIMING CHART 1-②.) A diode, which is an input protection element, is connected between the EN pin
and V
IN pin. Therefore, if the EN pin is applied voltage that exceeds VIN, the current will flow to VIN through the diode. For
avoiding any damage to the IC, please use this IC within the stated maximum ratings (V
SS -0.3 ~ VIN +0.3) on the EN pin.
<ENB Pin>
In case where the watchdog function is not used, when the ENB pin input driven to high level, only the watchdog function is
forced off while the detect voltage circuit remains operation. For using the watchdog function, the ENB pin should be used in
low level. Even after the input voltage and the ENB pin voltage are driven back low, the RESETB pin output maintains the
detection state for the release delay time (t
DR). (Refer to the TIMING CHART 2-①.) The watchdog function recovers
immediately when the input voltage becomes higher than the release voltage and the ENB pin voltage driven from high to low
level. (Refer to the TIMING CHART 2-②.) A diode, which is an input protection element, is connected between the ENB pin
and V
IN pin. Therefore, if the ENB pin is applied voltage that exceeds VIN, the current will flow to VIN through the diode. For
avoiding any damage to the IC, please use this IC within the stated maximum ratings (VSS -0.3 ~ VIN +0.3) on the ENB pin.
<Release Delay Time>
Release delay time (t
DR) is the time that elapses from when the VIN pin reaches the release voltage, or when the watchdog
timeout period expires with no rising signal applied to the WD pin, until the RESETB pin output is released from the detection
state. Five release delay time (t
DR) watchdog timeout period settings are available in 400ms, 200ms, 100ms, 50ms, and
3.13ms.
<Detect Delay Time>
Detect Delay Time (t
DF) is the time that elapses from when the VIN pin voltage falls to the detect voltage until the RESETB pin
output goes into the detection state.
