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Distributed Arithmetic FIR (DA-FIR) Filter Generator
Overview
The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP
implements a highly configurable, multi-channel DA-FIR filter, using distributed
arithmetic algorithms implemented in FPGA Look Up Table (LUT) or Embedded Block
Memory (EBR) to efficiently support the sum-of-product calculations required to perform
the filter function. These techniques generate very area-efficient utilization of the FPGA
LUTs while enabling savings of multiply-accumulate blocks (sysDSP) for other design logic. As a result, the DA-FIR Filter
Generator IP core is extremely useful for implementing custom DSP blocks in Lattice FPGAs. Please refer to the user's guide to
determine which cores are available for each device family.
Features
Variable number of taps up to 1024
Multi-channel support (up to 32 channels)
Polyphase interpolation/decimation filters
Halfband filters
Interpolation and Decimation ratios from 2 to 32
Input data widths from 4 to 32 bits
Coefficient widths from 4 to 32 bits
Signed or unsigned data and coefficients
Selectable rounding: truncation, rounding away from zero,
convergent rounding
Optional saturation logic for overflow handling
Full precision arithmetic
Specification of fractional inputs and outputs
Support for both serial and parallel filters, with user
specified degree of parallelism.
Configurable pipelining to increase performance
Optimizations based on filter characteristics (symmetry and
halfband).
Handshake signals to facilitate smooth interfacing
Performance and Resource Utilization
Channels Taps Interpolation DWidth Round SLICEs LUTs EBRs Registers Fmax
1 16 Disable 16 TRUN 290 348 - 476 318
1 9 Disable 8 TRUN 512 611 - 877 279
1 36 Enable 12 TRUN 600 709 - 883 308
LatticeECP3
1
1. Performance and utilization data are generated targeting a LFE3-70E-7FN484CES device using Lattice Diamond 1.0 and Synplify Pro D-
2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeECP3 family.
Channels Taps Interpolation DWidth Round SLICEs LUTs EBRs Registers Fmax
1 16 Disable 16 TRUN 317 378 - 481 343
1 9 Disable 8 TRUN 550 655 - 887 310
LatticeECP2M/S
1
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