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AS7C32098A-10TIN

P1-P3P4-P6P7-P9P10-P10
®
AS7C32098A
2/17/06, v 1.1 Alliance Semiconductor P. 4 of 10
Key to switching waveforms
Read waveform 1 (address controlled)
5,6,8
Read cycle (over the operating range)
2,8
Parameter Symbol
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time
t
RC
10 –12–15–20– ns
Address access time
t
AA
– 10–12–15–20ns
Chip enable (CE
) access time
t
ACE
– 10–12–15–20ns
Output enable (OE
) access time
t
OE
– 4–5–6–7ns
Output hold from address change
t
OH
3 –3–3–3–ns4
CE
Low to output in low Z
t
CLZ
3 –3–3–3–ns3,4
CE
High to output in high Z
t
CHZ
– 5–6–7–9ns3,4
OE
Low to output in low Z
t
OLZ
0 –0–0–0–ns3,4
OE
High to output in high Z
t
OHZ
– 5–6–7–9ns3,4
LB
, UB access time
t
BA
– 5–6–7–8ns
LB
, UB Low to output in low Z
t
BLZ
0 –0–0–0–ns
LB
, UB High to output in high Z
t
BHZ
– 5–6–7–9ns
Power up time
t
PU
0 –0–0–0–ns4
Power down time
t
PD
– 10–12–15–20ns4
Undefined/don’t careFalling inputRising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data validPrevious data valid
®
AS7C32098A
2/17/06, v 1.1 Alliance Semiconductor P. 5 of 10
Read waveform 2 (CE, OE, UB, LB controlled)
5,7,8
Write cycle (over the operating range)
9
Parameter Symbol
–10 –12 –15 –20
Unit NoteMin Max Min Max Min Max Min Max
Write cycle time
t
WC
10–12–15–20– ns
Chip enable (CE)
to write end
t
CW
7–8–10–12–ns
Address setup to write end
t
AW
7–8–10–12–ns
Address setup time
t
AS
0–0–0–0–ns
Write pulse width (OE
= High)
t
WP1
7–8–10–12–ns
Write pulse width (OE
= Low)
t
WP2
10–12–15–20– ns
Write recovery time
t
WR
0–0–0–0–ns
Address hold from end of write
t
AH
0–0–0–0–ns
Data valid to write end
t
DW
5–6 7–9–ns
Data hold time
t
DH
0–0–0–0–ns3,4
Write enable to output in High-Z
t
WZ
05060709ns3,4
Output active from write end
t
OW
3–3–3–3–ns3,4
Byte enable Low to write end
t
BW
7–8–10–12–ns3,4
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
CHZ
t
BHZ
t
ACE
t
CLZ
Address
OE
CE
LB, UB
Data
OUT
®
AS7C32098A
2/17/06, v 1.1 Alliance Semiconductor P. 6 of 10
Write waveform 1(WE controlled)
9
Write waveform 2 (CE controlled)
9
Address
CE
LB, UB
WE
Data
IN
Data
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data undefined
High Z
Data valid
t
WR
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data
OUT
Data undefined
High Z High Z
t
AS
t
AW
Data valid
t
CLZ
t
WR
P1-P3P4-P6P7-P9P10-P10

AS7C32098A-10TIN

Mfr. #:
Buy AS7C32098A-10TIN
Manufacturer:
Alliance Memory
Description:
SRAM 2M, 3.3V, 10ns FAST 128K x 16 Asyn SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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