Expand menu
Hello, Sign in
My Account
0
Cart
Home
Products
Sensors
Semiconductors
Passive Components
Connectors
Power
Electromechanical
Optoelectronics
Circuit Protection
Integrated Circuits - ICs
Main Products
Manufacturers
Blog
Services
About OMO
About Us
Contact Us
Check Stock
AS7C32098A-20TINTR
P1-P3
P4-P6
P7-P9
P10-P10
®
AS7C32098A
2/17/06, v 1.1
Alliance Semiconductor
P. 4 of 10
Key to switching waveforms
Read waveform 1 (address controlled)
5,6,8
Read cycle (over the operating range)
2,8
Parameter
Symbol
–10
–12
–15
–20
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
1
0
–
1
2–1
5–2
0–
n
s
Address access time
t
AA
–
1
0
–1
2–1
5–2
0
n
s
Chip enable (CE
) access time
t
ACE
–
1
0
–1
2–1
5–2
0
n
s
Output enable (OE
) access time
t
OE
–
4
–5–6–7
n
s
Output hold from address chang
e
t
OH
3
–
3–3–3–
n
s
4
CE
Low to output
in low Z
t
CLZ
3
–
3–3–3–
n
s
3
,
4
CE
High to output in high Z
t
CHZ
–
5
–6–7–9
n
s
3
,
4
OE
Low to output
in low Z
t
OLZ
0
–
0–0–0–
n
s
3
,
4
OE
High to
output in h
igh Z
t
OHZ
–
5
–6–7–9
n
s
3
,
4
LB
, UB
access time
t
BA
–
5
–6–7–8
n
s
LB
, UB
Low to output in low Z
t
BLZ
0
–
0–0–0–
n
s
LB
, UB
High to output in high Z
t
BHZ
–
5
–6–7–9
n
s
Power up time
t
PU
0
–
0–0–0–
n
s
4
Power down time
t
PD
–
1
0
–1
2–1
5–2
0
n
s
4
Undefined/don’t care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data valid
Previous data valid
®
AS7C32098A
2/17/06, v 1.1
Alliance Semiconductor
P. 5 of 10
Read waveform 2 (CE
, OE
, UB, LB
controlled)
5,7,8
Write cycle (over the operating range)
9
Parameter
Symbol
–10
–12
–15
–20
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
W
rite cycle time
t
WC
1
0–1
2–1
5
–
2
0
–
n
s
Chip enable (CE)
to write end
t
CW
7–8–
1
0
–
1
2
–n
s
Address setup to write end
t
AW
7–8–
1
0
–
1
2
–n
s
Address setup time
t
AS
0
–
0
–
0–0–
n
s
W
rite pulse width (OE
= High)
t
WP1
7–8–
1
0
–
1
2
–n
s
W
rite pulse width (OE
= Low)
t
WP2
1
0–1
2–1
5
–
2
0
–
n
s
W
rite recovery time
t
WR
0
–
0
–
0–0–
n
s
Address hold from end of write
t
AH
0
–
0
–
0–0–
n
s
Data valid to write end
t
DW
5
–
6
7–9–
n
s
Data hold
time
t
DH
0
–
0
–
0–0–
n
s
3
,
4
W
rite enable to output in High-Z
t
WZ
0
5
0
6
0709
n
s
3
,
4
Output active from write end
t
OW
3
–
3
–
3–3–
n
s
3
,
4
Byte enable Low to write end
t
BW
7–8–
1
0
–
1
2
–n
s
3
,
4
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
CHZ
t
BHZ
t
ACE
t
CLZ
Address
OE
CE
LB
, UB
Data
OUT
®
AS7C32098A
2/17/06, v 1.1
Alliance Semiconductor
P. 6 of 10
Write waveform 1(WE
controlled)
9
Write waveform 2 (CE controlled)
9
Address
CE
LB
, UB
WE
Data
IN
Data
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data undefined
High Z
Data valid
t
WR
Address
CE
LB
, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data
OUT
Data undefined
High Z
High Z
t
AS
t
AW
Data valid
t
CLZ
t
WR
P1-P3
P4-P6
P7-P9
P10-P10
AS7C32098A-20TINTR
Mfr. #:
Buy AS7C32098A-20TINTR
Manufacturer:
Alliance Memory
Description:
SRAM 2M, 3.3V, 20ns, FAST 128K x 16 Asyn SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
T/T
Paypal
Visa
MoneyGram
Western
Union
Products related to this Datasheet
AS7C32098A-10TCN
AS7C32098A-10TCNTR
AS7C32098A-12TCN
AS7C32098A-20TIN
AS7C32098A-15TCN
AS7C32098A-15TIN
AS7C32098A-12TIN
AS7C32098A-20TCN
AS7C32098A-12TINTR
AS7C32098A-15TINTR
AS7C32098A-10TINTR
AS7C32098A-10TIN
AS7C32098A-20TCNTR
AS7C32098A-15TCNTR
AS7C32098A-20TINTR
AS7C32098A-12TCNTR