CY28RS400
Document #: 38-07637 Rev. *B Page 6 of 19
0 1 Reserved Reserved
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 CLKREQ# CLKREQ# drive mode
0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when
stopped
6 0 CPU CPU pd drive mode
0 = CPU clocks driven when power down, 1 = CPU clocks tri-state
5 1 SRC SRC pd drive mode
0 = SRC clocks driven when power down, 1 = SRC clocks tri-state
4 0 CPU CPU_STOP# drive mode
0 = CPU clocks driven , 1 = CPU clocks tri-state
3 1 CPU2 Allow control of CPU2 with CPU_STOP#
0 = CPU2 is free running, 1 = CPU2 is stopped with CPU_STOP#
2 1 CPU1 Allow control of CPU1 with CPU_STOP#
0 = CPU1 is free running, 1 = CPU1 is stopped with CPU_STOP#
1 1 CPU0 Allow control of CPU0 with CPU_STOP#
0 = CPU0 is free running, 1 = CPU0 is stopped with CPU_STOP#
0 1 Reserved Reserved
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ0 control
1 = SRC[T/C]5 stoppable by CLKREQ#0 pin
0 = SRC[T/C]5 free running
6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#0 control
1 = SRC[T/C]4 stoppable by CLKREQ#0 pin
0 = SRC[T/C]4 free running
5 0 SRC[T/C]3 SRC[T/C]3 CLKREQ#0 control
1 = SRC[T/C]3 stoppable by CLKREQ#0 pin
0 = SRC[T/C]3 free running
4 0 SRC[T/C]2 SRC[T/C]2 CLKREQ#0 control
1 = SRC[T/C]2 stoppable by CLKREQ#0 pin
0 = SRC[T/C]2 free running
3 0 SRC[T/C]1 SRC[T/C]1 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
2 0 SRC[T/C]0 SRC[T/C]0 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
1 1 Reserved Reserved
0 1 Reserved Reserved
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ#1 control
1 = SRC[T/C]5 stoppable by CLKREQ#1 pin
0 = SRC[T/C]5 free running
6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#1 control
1 = SRC[T/C]4 stoppable by CLKREQ#1 pin
0 = SRC[T/C]4 free running
Byte 2: Control Register 2 (continued)
Bit @Pup Name Description
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