MIC2185BM Datasheet MIC2185YQS, MIC2185YM, MIC2185YM-TR | P10-P12

MIC2185 Micrel, Inc.

MIC2185 10 October 2005

PWM Operation

PWM ModeWaveform

TIME (1µs/div)

Switch NodeVoltage

(Low Side FET Drain)

5V/div

= 3.3V

High Side FET

Gate Drive

5V/div

Low Side FET

Gate Drive

5V/div

Inductor Current

1A offset; 0.5A/div

OUT

RippleVoltage

200mV/div

OUT

= 5V I

OUT

= 0.75A

Figure 5 - PWM mode waveforms

Figure 5 shows typical waveforms for PWM mode of operation.

The gate drive signal turns on the external low side MOSFET,

Q1, allowing the inductor current to ramp up. When the low

side MOSFET turns off and the high side MOSFET, Q2, turns

on, current ﬂowing in the inductor forces the MOSFET drain

voltage to rise until the is clamped at approximately the output

voltage. The MIC2185 uses current mode control to improve

output regulation and simplify compensation of the control

loop. Current mode control senses both the output voltage

(outer loop) and the inductor current (inner loop). It uses the

inductor current and output voltage to determine the duty

cycle (D) of the buck converter. Sampling the inductor current

effectively removes the inductor from the control loop, which

simpliﬁes compensation. A simpliﬁed current mode control

diagram is shown in ﬁgure 6.

I_inductor

PER

COMP

Gate Drive at OUTN

I_inductor

Gate Driver

I_inductor

Voltage

Divider

REF

Figure 6. PWM Control Loop

A block diagram of the MIC2185 PWM current mode control

loop is shown in Figure 1. The inductor current is sensed by

measuring the voltage across a resistor, Rsense. The current

sense ampliﬁer buffers and ampliﬁes this signal. A ramp is

added to this signal to provide slope compensation, which is

required in current mode control to prevent unstable operation

at duty cycles greater than 50%.

A transconductance ampliﬁer is used as an error ampliﬁer,

which compares an attenuated output voltage with a refer-

ence voltage. The output of the error ampliﬁer is compared

to the current sense waveform in the PWM block. When the

current signal rises above the error voltage, the comparator

turns off the low side drive. The error signal is brought out to

the COMP pin (pin 4) allowing the use of external components

to stabilize the voltage loop.

Current Sensing and Overcurrent Protection

The inductor current is sensed during the switch on time by

a current sense resistor located between the source of the

MOSFET, Q1 and ground (R

SENSE

in Figure 1). Exceeding

the current limit threshold will immediately terminate the

gate drive of the N-channel MOSFET. This forces the Q1 to

operate at a reduced duty cycle, which reduces the output

voltage. In a boost converter, the overcurrent limit will

not protect the power supply or load during a severe

overcurrent condition or short circuit condition. If the

output is short-circuited to ground, current will ﬂow from the

input, through the inductor and output diode,D1, to ground.

Only the impedance of the source and components limits

the current.

The minimum input voltage, maximum output power and

the minimum value of the current limit threshold determine

the value of the current sense resistor. The two switch, syn-

chronous operation of the MIC2185 forces the converter to

always operate in the continuous mode because current can

ﬂow both ways through the high side P-channel MOSFET.

The equations below will help to determine the current sense

resistor value.

Maximum Peak Current

The peak inductor current is equal to the average inductor

current plus one half of the peak to peak inductor current.

The peak inductor current is:

I I

V I

V V

2 V

fs L

IND(pk) IND(ave) IND(pp)

IND(pk)

O O

= + ×

× −

( )

× × ×

where:

is the maximum output current

is the output voltage

is the minimum input voltage

L is the value of the boost inductor

is the switching frequency

η is the efﬁciency of the boost converter

is the voltage across the inductor

may be approximated as V

for higher input voltage.

However, the voltage drop across the inductor winding

resistance and low side MOSFET on-resistance must be

accounted for at the lower input voltages that the MIC2185

can operate at:

October 2005 11 MIC2185

MIC2185 Micrel, Inc.

V V

V I

R R

L IN

O O

WINDING DS(ON)

= −

× +

( )

where:

WINDING

is the winding resistance of the inductor

DS(ON)

is the on resistance of the low side switching

MOSFET

The maximum value of current sense resistor is:

SENSE

IND(pk)

where:

SENSE

is the minimum current sense threshold of

the CSH pin

The current sense pin, CSH, is noise sensitive due to the

low signal level. The current sense voltage measurement

is referenced to the signal ground pin of the MIC2185. The

current sense resistor ground should be located close to the

IC ground. Make sure there are no high currents ﬂowing

in this trace. The PCB trace between the high side of the

current sense resistor and the CHS pin should also be short

and routed close to the ground connection. The input to the

internal current sense ampliﬁer has a 30nS dead time at the

beginning of each switching cycle. This dead time prevents

leading edge current spikes from prematurely terminating the

switching cycle. A small RC ﬁlter between the current sense

pin and current sense resistor may help to attenuate larger

switching spikes or high frequency switching noise. Adding

the ﬁlter slows down the current sense signal, which has the

effect of slightly raising the overcurrent limit threshold.

MOSFET Gate Drive

The MIC2185 synchronous boost converter drives both a

high side and low side MOSFET. The low side drive, OUTN,

drives an n-channel MOSFET. The high-side drive, OUTP,

is designed to switch a p-channel MOSFET (the p-channel

MOSFET doesn't require a bootstrap circuit which would

be needed to drive an n-channel MOSFET). The V

P pin

must be connected to the output, which provides power to

drive the high and low side MOSFETs. In skip mode, the

high side MOSFET is disabled by forcing the OUTP pin to

be high (equal to V

OUT

MOSFET Selection

In a boost converter, the V

of the MOSFET, Q1, is ap-

proximately equal to the output voltage. The maximum Vds

rating of the MOSFET must be high enough to allow for ring-

ing and spikes. The MIC2185 input voltage range is 2.9V to

14V. MOSFETs with 20V and 30V V

ratings are ideal for

use with this part.

The n-channel gate drive voltage is supplied by the OUTN

output. At startup in a boost converter, the output voltage

equals the input voltage. The V

threshold voltage of the

n-channel MOSFET must be low enough to operate at the

minimum input voltage to guarantee the boost converter will

start up. The p-channel MOSFET must have a minimum

threshold voltage equal to or lower than the output voltage.

Five volt threshold (logic level) MOSFETs are recommended

for the p-channel MOSFET. Ringing in the gate drive signal

may cause MOSFETs with lower gate thresholds to errone-

ously turn on.

There is a limit to the maximum amount of gate charge the

MIC2185 will drive. Higher gate charge will slow down the

turn-on and turn-off times of the MOSFETs. The MOSFET’s

must be able to completely turn on and off within the driver

non-overlap time or shoot-through will occur.

MOSFET gate charge is also limited by power dissipation in

the MIC2186. The power dissipated by the gate drive circuitry

is calculated below:

GATE_DRIVE

GATE

· V

P · f

where: Q

GATE

is the total gate charge of both of the external

n- and p-channel MOSFETs.

The graph in Figure 7 shows the total gate charge which can

be driven by the MIC2185 over the input voltage range, for

different values of switching frequency.

100

120

140

3 5 7 9 11 13

INPUT VOLTAGE (V)

Frequency vs.

Maximum Gate Charge

200kHz

300kHz

400kHz

500kHz

600kHz

Figure 7 - MIC2185 Frequency vs. Max. Gate Charge

External Schottky Diode

An external boost diode in parallel with the high side MOSFET

is used to keep the inductor current ﬂow continuous during

the non-overlap time when both MOSFETs are turned off.

Although the average current through this diode is small,

the diode must be able to handle currents equal to the peak

inductor current. This peak current is calculated in the Cur-

rent Limit section of this speciﬁcation

The reverse voltage requirement of the diode is:

V V

DIODE_RRM OUT

For the MIC2185, Schottky diodes with a 30V or 40V rating

are recommended. Schottky diodes with lower reverse volt-

age ratings have higher reverse leakage current which will

cause ringing and excessive power dissipation in the diode

and low side MOSFET.

The external Schottky diode is not necessary for circuit

operation since the high side MOSFET contains a parasitic

body diode. However, the body diode has a relatively slow

reverse recovery time and a relatively high forward voltage

drop. The lower forward voltage drop of the Schottky diode

both prevents the parasitic diode from turning on and im-

proves efﬁciency. The lack of a reverse recovery mechanism

in a Schottky diode causes less ringing than the MOSFET's

parasitic diode. Depending on the circuit components and

operating conditions, an external Schottky diode will improve

the converter efﬁciency by

% to 1%.

MIC2185 Micrel, Inc.

MIC2185 12 October 2005

Reference, Enable and UVLO Circuits

The output drivers are enabled when the following conditions

are satisﬁed:

• The VDD voltage (pin 10) is greater than its

undervoltage threshold.

• The voltage on the Enable pin is greater than

the Enable /UVLO threshold.

The internal bias circuitry generates a 1.245V bandgap

reference for the voltage error ampliﬁer and a 3V V

volt-

age for the internal supply bus. The reference voltage in the

MIC2185 is buffered and brought out to pin 8. The VREF

pin must be bypassed to GND (pin 4) with a 0.1µF capaci-

tor. The VDD pin must be decoupled to ground with a 1µF

ceramic capacitor.

The Enable pin (pin 7) has two threshold levels, allowing the

MIC2185 to shut down in a micro-current mode, or turn off

output switching in standby mode. Below 0.9V (typical), the

device is forced into a low-power shutdown. If the enable pin

is between 0.9V and 1.5V (typical) the output gate drive is

disabled but the internal circuitry is powered on and the soft

start pin voltage is forced low. There is typically 140mV of

hysteresis below the 1.5V threshold to insure the part does

not oscillate on and off due to ripple voltage on the input.

Raising the Enable voltage above the UVLO threshold of 1.5V

enables the output drivers and allows the soft start capacitor

to charge. The Enable pin may be pulled up to V

Oscillator & Sync

The internal oscillator is self-contained and requires no

external components. The f/2 pin allows the user to select

from two switching frequencies. A low level sets the oscilla-

tor frequency to 400kHz and a high level sets the oscillator

frequency to 200kHz. The maximum duty cycle for both

frequencies is typically 85%. The minimum pulse width in-

creases but does not double when the frequency is changed

from 400kHz to 200kHz. This means the minimum duty cycle

is slightly lower at 200kHz. This may be important as the

input voltage approaches the output voltage. At lower duty

cycles, the input voltage can be closer to the output voltage

without the output rising out of regulation.

A frequency foldback mode is enabled if the voltage on the

Feedback pin (pin 6) is less than 0.3V. In frequency foldback

the oscillator frequency is reduced by approximately a factor

of 4. For the 400kHz setting, the oscillator runs at 100khz in

frequency foldback. For a 200kHz setting the oscillator runs

at approximately 50kHz.

The SYNC input (pin 11) allows the MIC2185 to synchronize

with an external CMOS or TTL clock signal. The rising edge

of the sync signal generates a reset signal in the oscillator,

which turns off the high side gate drive output. The low side-

drive then turns on, restarting the switching cycle. The sync

signal is inhibited when the controller operates in skip mode

or frequency foldback. The sync signal frequency must be

greater than the maximum speciﬁed free running frequency of

the MIC2185. If the synchronizing frequency is lower, double

pulsing of the gate drive outputs will occur. When not used,

the sync pin must be connected to ground.

Figure 8 shows the timing between the external sync signal,

low side-drive and the high side drive when the f/2 pin is low.

The delay between the rising edge of the sync signal and the

turn on of the low side gate drive is typically 900ns when the

f/2 pin is high and 600ns when the f/2 pin is low.

Sync Waveform

TIME (500ns/div)

Sync Input

2V/div

600ns

Switch NodeVoltage

(Low Side FET Drain)

5V/div

High Side FET

Gate Drive

5V/div

Low Side FET

Gate Drive

5V/div

Figure 8. Sync Waveforms

The maximum recommended output switching frequency is

600kHz. Synchronizing to higher frequencies may be pos-

sible, however there are some concerns. As the switching

frequency is increased, the switching period decreases.

The minimum on time in the MIC2185 becomes a greater

part of the total switching period. This may prevent proper

operation as Vin approaches Vout and may also minimize

the effectiveness of the current limit circuitry. The maximum

duty cycle decreases as the sync frequency is increased.

Figure 9 shows the relationship between the minimum and

maximum duty cycle and frequency.

100

0 100 200 300 400 500 600

FREQUENCY (kHz)

MIC2185 Sync Frequency

vs. Dut

cle

F /2 HIG H

F /2 LOW

F /2 HIG H

Figure 9

Table 1 summarizes the differences in the MIC2185 for the

two different states of the f/2 pin.

F/2 pin Switching Typical Typical t

OFF

Level Frequency Max Duty Min. Duty SKIP Mode

(kHz) cycle (%) cycle (%)

0 400 85 6 1µs

1 200 85 6 2µs

MIC2185 Table 1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

MIC2185BM

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