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536EC312M500DG

P1-P3P4-P6P7-P9P10-P12
Si535/536
4 Rev. 1.2
Figure 1. Si535/536 Typical Phase Noise at 156.25 MHz
Table 4. CLK± Output Phase Jitter
Parameter Symbol Test Condition Min Typ Max Unit
LVPECL/LVDS Phase Jitter*
(RMS)
J
10 kHz to 1 MHz (data center) — 0.19 0.35 ps
12 kHz to 20 MHz brickwall — 0.25 0.40 ps
*Note: Applies to output frequencies: 156.25 MHz.
Table 5. CLK± Output Period Jitter
Parameter Symbol Test Condition Min Typ Max Unit
LVPECL/LVDS Period Jitter*
J
PER
RMS — 2 — ps
Peak-to-Peak — 14 — ps
*Note: N = 1000 cycles.
Si535/536
Rev. 1.2 5
Table 6. Environmental Compliance
The Si535/536 meets the following qualification test requirements.
Parameter Conditions/Test Method
Mechanical Shock
MIL-STD-883, Method 2002
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Gross & Fine Leak
MIL-STD-883, Method 1014
Resistance to Solder Heat
MIL-STD-883, Method 2036
Moisture Sensitivity Level
J-STD-020, MSL1
Contact Pads
Gold over Nickel
Table 7. Thermal Characteristics
(Typical values TA = 25 ºC, V
DD
=3.3V)
Parameter Symbol Test Condition Min Typ Max Unit
Thermal Resistance Junction to Ambient
JA
Still Air — 84.6 — °C/W
Thermal Resistance Junction to Case
JC
Still Air — 38.8 — °C/W
Ambient Temperature T
A
–40 — 85 °C
Junction Temperature T
J
——125°C
Table 8. Absolute Maximum Ratings
1
Parameter Symbol Rating Unit
Maximum Operating Temperature
T
AMAX
85 °C
Supply Voltage, 2.5/3.3 V Option
V
DD
–0.5 to +3.8 V
Input Voltage (any input pin)
V
I
–0.5 to V
DD
+ 0.3 V
Storage Temperature
T
S
–55 to +125 °C
ESD Sensitivity (HBM, per JESD22-A114)
ESD 2500 V
Soldering Temperature (Pb-free profile)
2
T
PEAK
260 °C
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
t
P
20–40 seconds
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Si535/536
6 Rev. 1.2
2. Pin Descriptions
Table 9. Pinout for Si535 Series
Pin Symbol Function
1 NC No connection
2OE
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
3 GND Electrical and Case Ground
4 CLK+ Oscillator Output
5 CLK– Complementary Output
6V
DD
Power Supply Voltage
*Note: OE includes a 17 k pullup resistor to V
DD
.
Table 10. Pinout for Si536 Series
Pin Symbol Function
1OE
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
2 No connection No connection
3 GND Electrical and Case Ground
4 CLK+ Oscillator Output
5 CLK– Complementary output
6V
DD
Power Supply Voltage
*Note: OE includes a 17 k pullup resistor to V
DD
.
(Top View)
Si535
Si536
P1-P3P4-P6P7-P9P10-P12

536EC312M500DG

Mfr. #:
Buy 536EC312M500DG
Manufacturer:
Silicon Labs
Description:
Standard Clock Oscillators Differential/single-ended; single frequency XO; OE pin 2; 10-1417 MHz
Lifecycle:
New from this manufacturer.
Delivery:
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