3
ATF1500ABV
0723I–08/01
The ATF1500ABV’s 100% connected global input and feedback architecture simplifies logic
placement and eliminates pinout changes due to design changes. Any Macrocell may be con-
nected to any I/O pin.
The ATF1500ABV has 32 bi-directional I/O pins and four dedicated input pins. Each dedicated
input pin can also serve as a global control signal: register clock, register reset or output
enable. Each of these control signals can be selected for use individually within each
macrocell.
Each of the 32 logic macrocells generates a buried feedback, which goes to the global bus.
Each input and I/O pin also feeds into the global bus. Because of this global busing, each of
these signals is always available to all 32 macrocells in the device.
Each macrocell also generates a foldback logic term, which goes to a regional bus. All signals
within a regional bus are connected to all 16 macrocells within the region.
Cascade logic between macrocells in the ATF1500ABV allows fast, efficient generation of
complex logic functions. The ATF1500ABV contains four such logic chains, each capable of
creating sum term logic with a fan-in of up to 40 product terms.
Bus-friendly
Pin-keeper
Input and I/Os
All input and I/O pins on the ATF1500ABV have programmable “data-keeper” circuits. If acti-
vated, when any pin is driven high or low and then subsequently left floating, it will stay at that
previous high or low level.
This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels
that cause unnecessary power consumption and system noise. The keeper circuits eliminate
the need for external pull-up resistors and eliminate their DC power consumption.
Pin-keeper circuits can be disabled. Programming is controlled in the logic design file. Once
the pin-keeper circuits are disabled, normal termination procedures are required for unused
inputs and I/Os.
Speed/Power
Management
The ATF1500ABV has several built-in speed and power management features. The
ATF1500ABV contains circuitry that automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only reduces power consumption dur-
ing inactive periods, but also provides proportional power savings for most applications
running at system speeds below 10 MHz.
All ATF1500ABVs also have an optional pin-controlled power-down mode. In this mode, cur-
rent drops to typically 2 mA. When the power-down option is selected, the PD pin is used to
power-down the part. The power-down option is selected in the design source file. When
enabled, the device goes into power-down when the PD pin is high. In the power-down mode,
all internal logic signals are latched and held, as are any enabled outputs. All pin transitions
are ignored until the PD is brought low. When the power-down feature is enabled, the PD can-
not be used as a logic input or output. However, the PD pin’s macrocell may still be used to
generate buried foldback and cascade logic signals.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
