AD976AANZ Datasheet AD976ARZ, AD976BRZ, AD976ABRSZ | P13-P15

AD976/AD976A

–13–

REV. C

DC CODE UNCERTAINTY

Ideally, a fixed dc input should result in the same output code

for repetitive conversions; however, as a consequence of un-

avoidable circuit noise within the wideband circuits of the ADC,

a range of output codes may occur for a given input voltage.

Thus, when a dc signal is applied to the AD976/AD976A input,

and 10,000 conversions are recorded, the result will be a distri-

bution of codes as shown in Figure 19. This histogram shows a

bell-shaped curve consistent with the Gaussian nature of ther-

mal noise. The histogram is approximately seven codes wide.

The standard deviation of this Gaussian distribution results in a

code transition noise of 1 LSB rms.

4000

3500

–3

2000

1500

1000

500

3000

2500

–2 –1 0 1 2 3 4

Figure 19. Histogram of 10,000 Conversions of a DC Input

MICROPROCESSOR INTERFACING

The AD976/AD976A is ideally suited for traditional dc mea-

surement applications supporting a microprocessor and ac signal

processing applications interfacing to a digital signal processor.

The AD976/AD976A is designed to interface with a 16-bit data

bus and provides all output data bits in a single read cycle. A

variety of external buffers can be used with the AD976/AD976A

to prevent bus noise from coupling into the ADC. The following

sections illustrate the use of the AD976/AD976A with the

MC68000 and 8051 microcontrollers and the TMS320C25 and

ADSP-2111 signal processors.

MC68000 Interface

Figure 20 shows a general interface diagram for the MC68000

16-bit microprocessor to the AD976/AD976A. In Figure 20,

conversion is initiated by bringing CSA low (i.e., writing to the

appropriate address). This allows the processor to maintain

control over the complete conversion process.

ADDRESS BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

DATA BUS

DB15

DB0

BUSY

AD976/

AD976A

R/C

BUS

74HC374

Q15

D15

CLK

ADDR

DECODE

A15

D15

68000

R/W

Figure 20. AD976/AD976A to 68000 Interface

250

150

100

200

NUMBER OF UNITS

0.2

0.3

0.4

0.6

0.7

0.8

1.0

1.1

1.2

1.4

1.5

1.6

1.8

1.9

2.0

2.2

2.3

2.4

2.6

2.7

2.8

3.0

3.1

3.2

POSITIVE DNL DISTRIBUTION – LSB

Figure 17. Typical Position DNL Distribution (1516 Units)

140

120

100

NUMBER OF UNITS

–1.2

NEGATIVE DNL DISTRIBUTION – LSB

–1.2

–1.1

–1

–0.9

–0.8

–0.7

–0.6

–0.5

–0.4

–0.3

–0.2

–0.1

Figure 18. Typical Negative DNL Distribution (1516 Units)

AD976/AD976A

–14–

REV. C

8051 Interface

Figure 21 illustrates the use of the AD976/AD976A with an

8051 microcontroller.

DB7

DB0

BYTE

BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

BUSY

AD976/

AD976A

8051

LATCH

BUS

AD0

AD7

A15

INT

R/C

ADDR

DECODE

Figure 21. AD976/AD976A to 8051 Interface

TMS320C25 Interface

Figure 22 shows an interface between the AD976/AD976A and

the TMS320C25.

TIMER

ADDRESS BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

DATA BUS

DB15

DB0

BUSY

AD976/

AD976A

R/C

ADDR

DECODE

A15

D15

TMS320C25

R/W

READY

STRB

NSC

INT

Figure 22. AD976/AD976A to TMS320C25 Interface

ADSP-2111 Interface

Figure 23 shows an interface to the ADSP-2111 signal processor.

In this example, CS is being used to control conversions and is

generated by an external timer. A conversion is initiated each

time the timer output goes low as long as you are not reading

from the AD976/AD976A and while the Flag Output (FO) pin

of the ADSP-2111 is low. When a conversion is complete, the

BUSY line will return high. With the IRQn pin programmed to

generate an interrupt on a high-to-low transition, an interrupt

will occur at the end of each conversion. The 16-bit result of the

conversion can be read from within the interrupt service routine

by first forcing FO high, then performing a read operation with

the AD976/AD976A.

ADDRESS BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

DATA BUS

DB15

DB0

BUSY

AD976/

AD976A

ADDR

DECODE

A13

D15

ADSP-2111

DMS

IRQn

TIMER

R/C

Figure 23. AD976/AD976A to ADSP-2111 Interface

POWER SUPPLIES AND DECOUPLING

The AD976/AD976A has two power supply input pins. V

ANA

and V

DIG

provide the supply voltages to the analog and digital

portions, respectively. V

ANA

is the +5 V supply for the on-chip

analog circuitry, and V

DIG

is the +5 V supply for the on-chip

digital circuitry. The AD976/AD976A is designed to be inde-

pendent of power supply sequencing and, thus, free from supply

voltage induced latch-up.

With high performance linear circuits, changes in the power

supplies can result in undesired circuit performance. Optimally,

well regulated power supplies should be chosen with less than

1% ripple. The ac output impedance of a power supply is a

complex function of frequency and it will generally increase with

frequency. Thus, high frequency switching, such as that encoun-

tered with digital circuitry, requires the fast transient currents

that most power supplies can not adequately provide. Such a

situation results in large voltage spikes on the supplies. To com-

pensate for the finite ac output impedance of most supplies,

charge “reserves” should be stored in bypass capacitors. This

will effectively lower the supplies impedance presented to the

AD976/AD976A V

ANA

and V

DIG

pins and reduce the magnitude

of these spikes. Decoupling capacitors, typically 0.1 µF, should

be placed close to the power supply pins of the AD976/AD976A

to minimize any inductance between the capacitors and the

ANA

and V

DIG

pins.

The AD976/AD976A may be operated from a single +5 V sup-

ply. When separate supplies are used, however, it is beneficial to

have larger capacitors, 10 µF, placed between the logic supply

DIG

) and digital common (DGND) and between the analog

supply (V

ANA

) and the analog common (AGND2). Additionally,

10 µF capacitors should be located in the vicinity of the ADC to

further reduce low frequency ripple. In systems where the device

will be subjected to harsh environmental noise, additional de-

coupling may be required.

AD976/AD976A

–15–

REV. C

GROUNDING

The AD976/AD976A has three ground pins; AGND1, AGND2

and DGND. The analog ground pins are the “high quality”

ground reference points and should be connected to the system

analog common. AGND2 is the ground to which most internal

ADC analog signals are referenced. This ground is most

susceptible to current induced voltage drops and thus must be

connected with the least resistance back to the power supply.

AGND1 is the low current analog supply ground and should be

the analog common for the external reference, input op amp

drive circuitry and the input resistor divider circuit. By applying

the inputs referenced to this ground, any ground variations will

be offset and have a minimal effect on the resulting analog input

to the ADC. The digital ground pin, DGND, is the reference

point for all of the digital signals that control the AD976/AD976A.

The AD976/AD976A can be powered with two separate power

supplies or with a single analog supply. When the system digital

supply is noisy or fast switching digital signals are present, it is

recommended to connect the analog supply to both the V

ANA

and V

DIG

pins of the AD976/AD976A and the system supply to

the remaining digital circuitry. With this configuration, AGND1,

AGND2, and DGND should be connected back at the ADC.

When there is significant bus activity on the digital output pins,

the digital and analog supply pins on the ADC should be sepa-

rated. This would eliminate any high speed digital noise from

coupling back to the analog portion of the AD976/AD976A.

In this configuration, the digital ground pin DGND should be

connected to the system digital ground and be separate from the

AGND pins.

BOARD LAYOUT

Designing with high resolution data converters requires careful

attention to board layout. Trace impedance is a significant issue.

A 1.22 mA current through a 0.5 Ω trace will develop a voltage

drop of 0.6 mV, which is 2 LSBs at the 16-bit level over the

20 volt full-scale range. Ground circuit impedances should be

reduced as much as possible since any ground potential differ-

ences between the signal source and the ADC appear as an error

voltage in series with the input signal. In addition to ground

drops, inductive and capacitive coupling needs to be considered.

This is especially true when high accuracy analog input signals

share the same board with digital signals. Thus, to minimize

input noise coupling, the input signal leads to V

and the signal

return leads from AGND should be kept as short as possible. In

addition, power supplies should also be decoupled to filter out

ac noise.

Analog and digital signals should not share a common path.

Each signal should have an appropriate analog or digital return

routed close to it. Using this approach, signal loops enclose a

small area, minimizing the inductive coupling of noise. Wide PC

tracks, large gauge wire and ground planes are highly recom-

mended to provide low impedance signal paths. Separate analog

and digital ground planes are also recommended with a single

interconnection point to minimize ground loops. Analog signals

should be routed as far as possible from high speed digital sig-

nals and should only cross them, if absolutely necessary, at right

angles.

In addition, it is recommended that multilayer PC boards be

used with separate power and ground planes. When designing

the separate sections, careful attention should be paid to the

layout.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

AD976AANZ

Mfr. #:

Buy AD976AANZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 16-Bit 200 kSPS Parallel I/O

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD976AANZ

AD976AANZ

Products related to this Datasheet