LT8631
11
8631fa
For more information www.linear.com/LT8631
OPERATION
The regulators’ maximum output current occurs when the
internal V
C
node is driven to its maximum clamp value
by the error amplifier. The value of the typical maximum
switch current is 2A. If the current demanded by the output
exceeds the maximum current dictated by the internal V
C
clamp, the TR/SS pin will be discharged, lowering the
regulation point until the output voltage can be supported
by the maximum current. Once the overload condition is
removed, the regulator will soft-start from the overload
regulation point.
EN/UV pin control or thermal shutdown will set the soft-
start latch, resulting in a complete soft-start sequence.
Comparators monitoring the FB pin voltage will pull the
PG pin low if the output voltage varies more the ±7.5%
from the feedback reference voltage. The PG comparators
have 1.9% of hysteresis.
In light load situations (low V
C
voltage), the LT8631 oper-
ates in Burst Mode to optimize efficiency. Between bursts,
all
circuitry associated with controlling the output switch
is shut down, reducing the input supply current to 16µA.
In a typical application, 16µA will be consumed from the
input supply when regulating with no load. The SYNC/
MODE pin is tied
low to use Burst Mode operation and can
be
tied to a logic high to use pulse-skipping mode. During
pulse-skipping mode and light loads, switch pulses are
skipped to regulate the output and the quiescent current
will be typically several hundred µA.
To improve efficiency across all loads, supply current to
internal circuitry is sourced from the V
OUT
pin when it’s
biased at 3.5V or above. If the V
OUT
pin is below 3.5V the
internal supply current is sourced from V
IN
.
The internal oscillator generates a clock signal at a fre-
quency determined
by the resistor connected from the RT
pin to ground. Alternatively, if a synchronization signal
is detected by the LT8631 SYNC/MODE pin, the internal
clock will be generated at the incoming frequency on the
rising edge of the synchronization pulse.
When the voltage on the V
C
node rises above the switching
threshold, the clock set-pulse sets the driver flip-flop, which
turns on the internal top power switch. This causes current
from V
IN
, through the top switch, inductor, and internal
sense resistor, to increase. When the voltage drop across
the internal sense resistor exceeds a predetermined level
set by
the voltage on the internal V
C
node, the flip-flop is
reset and the internal top switch is turned off. Once the
top switch is turned off the inductor will drive the volt
-
age at the SW pin low. The synchronous power switch
will turn on, decreasing the current in the inductor, until
the next clock cycle or the inductor current falls to zero.
However, if the internal sense resistor voltage exceeds
the predetermined level at the start of a clock cycle, the
flip-flop will not be set resulting in a further decrease in
the inductor current. Alternatively, if the current through
the inductor doesn't exceed the current demanded by the
V
C
voltage during the clock cycle, the top switch will stay
on until the required current is reached or the voltage on
the boost pin falls below its minimum required value.
Since the output current is controlled by the internal V
C
voltage, output regulation is achieved by the error amplifier
continuously adjusting the V
C
voltage.
