FM75 Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FM75 Rev. 1.0.8 11
Serial Data Bus Operation
General Operation
Writing to and reading from the FM75 registers is accom-
plished via the SMBus-compatible two-wire serial inter-
face. SMBus protocol requires that one device on the
bus initiates and controls all read and write operations.
This device is called the “master” device. The master
device also generates the SCL signal, which is the clock
signal for all other devices on the bus. All other devices
on the bus are called “slave” devices. The FM75 is a
slave device. Both the master and slave devices can
send and receive data on the bus.
During SMBus operations, one data bit is transmitted per
clock cycle. All SMBus operations follow a repeating nine
clock-cycle pattern that consists of eight bits (one byte)
of transmitted data followed by an acknowledge (ACK) or
not acknowledge (NACK) from the receiving device.
Note that there are no unused clock cycles during any
operation—therefore there must be no breaks in the
stream of
data and ACKs/NACKs during data transfers.
Conversely,
too few clock cycles can lead to incorrect
operation if an inadvertent 8-bit read from a 16-bit regis-
ter occurs.
For most operations, SMBus protocol requires the SDA
line to remain stable (unmoving) whenever SCL is HIGH—
i.e., transitions on the SDA line can only occur when SCL
is LOW. The exceptions to this rule are when the master
device issues a start or stop signal. The slave device
cannot issue a start or stop signal.
Start Condition: This condition occurs when the SDA
line transitions from HIGH to LOW while SCL is HIGH.
The master device uses this condition to indicate that a
data transfer is about to begin.
Stop Condition: This condition occurs when the SDA
line transitions from LOW to HIGH while SCL is HIGH.
The master device uses this condition to signal the end
of a data transfer.
Acknowledge and Not Acknowledge: When data is
transferred to the slave device, it sends an acknowledge
(ACK) after receiving every byte of data. A master device
sends an acknowledge (ACK) following only the first byte
read from a two-byte register. The receiving device
sends an ACK by pulling SDA LOW for one clock cycle.
Following the last byte, a master device sends a “not
acknowledge” (NACK) followed by a stop condition. A
NACK is indicated by leaving SDA HIGH during the clock
after the last byte.
Slave Address
Each slave device on the bus has a unique 7-bit address
so the master can identify which device is sending or
receiving data.
The FM75 address is as follows:
The four MSBs of the FM75 address are hardwired to
1001. The three LSBs are user configurable by tying the
A0, A1, and A2 pins to either V
DD
or ground. This pro-
vides eight different FM75 addresses, which allows up to
eight FM75s to be connected to the same bus.
Writing to and Reading from the FM75
All read and write operations must begin with a start sig-
nal generated by the master device. After the start condi-
tion, the master device must immediately send a slave
address (7 bits), followed by a read/write bit. If the slave
address matches the address of the FM75, the FM75
sends an ACK after receiving the read/write bit by pulling
the SDA line LOW for one clock cycle. Figures 11 -16
provide timing diagrams for all FM75 operations.
Setting the Pointer
For all operations, the pointer stored in the command
register must be pointing to the register (temperature,
configuration, T
OS
or T
HYST
) that is going to be written to
or read from. To change the pointer value in the com-
mand register, the read/write bit following the address
must be 0. This indicates that the master will write new
information into the command register.
After the FM75 sends an ACK in response to receiving
the address and read/write bit, the master device must
transmit an appropriate 8-bit pointer value, as explained
in the Registers section. The FM75 sends an ACK after
receiving the new pointer data.
The pointer set operation is illustrated in Figure 11. Any-
time a pointer set is performed, it must be immediately
followed by a read or write operation. Note that the six
MSBs of the pointer value must be zero. If the six MSBs
are not zero, the FM75 does not send an ACK and inter-
nally terminates the operation. The command register
retains the current pointer value between operations;
therefore, once a register is indicated, subsequent read
operations do not require a pointer set cycle. Write oper-
ations always require the pointer be reset.
1
0
0
1A1A2
A0
