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MAX8688ALETG+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
MAX8688
Digital Power-Supply Controller/Monitor
with PMBus Interface
______________________________________________________________________________________ 31
PMBUS_REVISION (98h)
The PMBUS_REVISION command returns the revision
of the PMBus specification to which the MAX8688 is
compliant.
The command has 1 data byte. Bits [7:5] indicate the
revision of PMBus specification Part I to which the
MAX8688 is compliant. Bits [4:0] indicate the revision of
PMBus specification Part II to which the MAX8688 is
compliant. The permissible values are shown in Table 7.
This command is read only.
The default PMBUS_REVISION value is 00h which indi-
cates that the MAX8688 is compliant with Part I Rev 1.0
and Part II Rev 1.0.
MFR_ID (99h)
The MFR_ID command returns the MAX8688 manufac-
turer’s identification.
The default MFR_ID value is 4D01h.
This command is read only.
MFR_MODEL (9Ah)
The MFR_MODEL command returns the MAX8688
model number.
The default MFR_MODEL value is 4101h.
This command is read only.
MFR_REVISION (9Bh)
The MFR_REVISION command reads the ASCII charac-
ters that contain the MAX8688 revision number with a
block read command.
The default MFR_REVISION value is 3201h.
This command is read only.
MFR_SMB_LOOPBACK (D0h)
The MFR_SMB_LOOPBACK command returns the data
word previously received by the MAX8688. The SMBus
master writes a data word to the MAX8688 using this
command and then retrieves the data word. A valid
communication channel is established if the master
reads back the same word.
Note that if another command is sent in between the write
MFR_SMB_LOOPBACK command and the read
MFR_SMB_LOOPBACK command, the MAX8688 returns
whatever last command data word it receives.
MFR_MODE (D1h)
The MFR_MODE command is used to configure the
MAX8688 to support manufacturer specific commands.
The MFR_MODE command is described in Table 8.
The default MFR_MODE value is 00h.
BITS [7:5]
PART I
REVISION
BITS [4:0]
PART II
REVISION
000 1.0 00000 1.0
Table 7. PMBus Revision Data Byte
Contents
BIT BIT NAME DESCRIPTION
15:8
Input Clock Time
Factor
This is equivalent to the number of external clock cycles provided to CLKIO in 100µs - 2.
MFR_MODE[15:8] = f
EXT_CLK
/10kHz - 2 where f
EXT_CLK
is the frequency of the external clock. For
example, when f
EXT_CLK
= 1MHz, f
EXT_CLK
/10kHz = 100, MFR_MODE[15:8] = 100 – 2 = 98. Valid
external input clock range is from 100kHz (MFR_MODE[15:8] = 8) to 2.5MHz (MFR_MODE[15:8] =
248).
These bits are ignored if the internal clock source is selected as the time base (Clock Source
Select bit = 0)
7 Clock Out Enable
The Clock Out Enable bit allows the output of a 1MHz reference clock to CLKIO for synchronizing
multiple MAX8688s. Setting this bit to 1 enables the 1MHz output on CLKIO. When this bit is cleared
to 0, no reference clock is outputted.
6 A3 Control Enable
Setting this bit to 1 enables A3/ONOFF to function as a POL ON/OFF input control. Clearing this bit to
0 ignores the A3/ONOFF state and the MAX8688 is controlled by the OPERATION command alone.
See the A3/ONOFF Operation section.
Table 8. MFR_MODE Bit Definition
MAX8688
Digital Power-Supply Controller/Monitor
with PMBus Interface
32 ______________________________________________________________________________________
MFR_VOUT_CORRECTION_RATE (D2h)
The MFR_VOUT_CORRECTION_RATE command sets
the frequency (Hz) at which the MAX8688 adjusts 1
LSB of DACOUT (0.5mV) after the voltage has entered
the regulation band.
Correction Rate = 10kHz/MFR_VOUT_CORRECTION_RATE
The 2 data bytes are formatted as positive integers. Valid
values are from 1 to 65535. Setting this value to 0 dis-
ables the DACOUT adjustment in the regulation band.
The default MFR_VOUT_CORRECTION_RATE value is
10 which is equivalent to a correction rate of 1kHz.
MFR_SAMPLE_RATE (D3h)
The MFR_SAMPLE_RATE command sets the frequency
(Hz) at which the POL output voltage, output current,
and temperature fault/warning conditions are monitored.
Monitor Sample Rate =10kHz/MFR_SAMPLE_RATE
The 2 data bytes are formatted as positive integers.
Valid values are from 1 to 65535. Setting this value to 0
disables all fault/warning monitoring.
The default MFR_SAMPLE_RATE value is 50 which is
equivalent to a sample rate of 200Hz.
BIT BIT NAME DESCRIPTION
5
EEPROM Lock
Enable
The EEPROM Lock Enable bit is used to protect external EEPROM data from being overwritten. When
this bit is set to 1, the STORE_DEFAULT_ALL command is ignored. The RESTORE_DEFAULT_ALL
command is still valid. When this bit is cleared to 0, the STORE_DEFAULT_ALL command initiates a
store configuration operation to the EEPROM attached to A1/SCLE and A2/SDAE.
4
Correction Bypass
Enable
Correction Bypass Enable. Setting this bit to 1 disables a correction algorithm made to voltage,
current, and temperature readings. Clearing this bit to 0 applies a correction algorithm to voltage,
current, and temperature measurement, thus resulting in high-accuracy readings. For optimal
operation, this bit should be cleared to 0.
3 Input Range Select
The Input Range Select bit determines the input range of RS+ and RS-. Setting this bit to 1 extends
the input range to 5.5V. Clearing this bit to 0 sets the input range to 2.048V.
Prior to setting any voltage-related values, the user application must first configure the desired input
range. All voltage-related commands use the selected input range to convert the commanded value
into internal register values.
It is not recommended to change the input range selection while the POL is operating, since all
voltage-related commands continue to refer to the input range that was in use when the commanded
voltage was received. This results in unpredictable and catastrophic operation.
2
ENOUT Polarity
Select
The ENOUT Polarity Select bit selects the ENOUT active-on polarity. Setting this bit to 1 configures the
ENOUT asserted on-state the same as the default startup state. Clearing this bit to 0 configures the
ENOUT deasserted off-state the same as the default startup state. In effect, writing a 1 to this bit
means that the asserted state of ENOUT is the default startup state. See the ENOUT Operation
section.
1
Feedback Mode
Select
The Feedback Mode Select bit determines the MAX8688 operation mode. When this bit is set to 1, the
MAX8688 operates in the feedback mode while when cleared to 0, the MAX8688 operates in the
REFIN mode.
0
Clock Source
Select
The Clock Source Select bit determines the MAX8688 reference clock time source. When the Clock
Source Select bit is set to 1, an external clock must be supplied to CLKIO and is used as the
MAX8688 reference clock. When this bit is cleared to 0, an internal clock is used.
Table 8. MFR_MODE Bit Definition (continued)
MAX8688
Digital Power-Supply Controller/Monitor
with PMBus Interface
______________________________________________________________________________________ 33
MFR_VOUT_PEAK (D4h)
The MFR_VOUT_PEAK command returns the maximum
actual measured (not commanded) output voltage in
volts across RS+ and RS-. If the filter mode is enabled,
instead of returning the instantaneous value, the filtered
output voltage is returned. To reset this value to 0, write
to this command with a data value of 0. Any other val-
ues written by this command are used as a comparison
for future peak updates.
The 2 data bytes are in DIRECT format. Valid values are
the same as VOUT_COMMAND.
The default MFR_VOUT_PEAK value is 0.
MFR_IOUT_PEAK (D5h)
The MFR_IOUT_PEAK command returns the maximum
measured output current in amperes across ISN+ and
ISN-. To reset this value to 0, write to this command with
a data value of 0. Any other values written by this com-
mand are used as a comparison for future peak updates.
The 2 data bytes are in DIRECT format. Valid values are
the same as IOUT_OC_FAULT_LIMIT.
The default MFR_IOUT_PEAK value is 00h.
MFR_TEMPERATURE_PEAK (D6h)
The MFR_TEMPERATURE_PEAK command returns the
maximum actual on-chip measured temperature in
degrees Celsius. To reset this value to its lowest value,
write to this command with a data value of 0FFFFh. Any
other values written by this command are used as a
comparison for future peak updates.
The 2 data bytes are in DIRECT format. Valid values are
the same as OT_FAULT_LIMIT.
The default MFR_TEMPERATURE_PEAK value is 00h.
MFR_FILTER_MODE (D7h)
The MFR_FILTER_MODE command is used to set V
OUT
sample count and sample delays.
Whenever filtering is enabled (MFR_FILTER_MODE[7:0]
not equal to 0), voltage-related readings are computed
as an average over the sample count. Fault and warning
limits are compared against the averaged value to
determine if a fault/warning has occurred. The Sample
Delay bit value (MFR_FILTER_MODE[15:8]) sets the
time between successive voltage readings. Note that
when filtering is disabled (MFR_FILTER_MODE[7:0] =
0), the Sample Delay bit value is ignored.
The default MFR_FILTER_MODE value is 00h (1
Sample Count bit and no delay). When filtering is in
progress, the PMBus command is ignored.
MFR_FAULT_STATUS (D8h)
When a warning or fault condition is detected, the
MAX8688 sets the corresponding bit in the
MFR_FAULT_STATUS register to 1 and notifies the host
using FLT assertion. The STATUS_BYTE is computed
from MFR_FAULT_STATUS[7:0].
This register is cleared to 0 together with the
STATUS_BYTE register by any of the fault/warning clear-
ing methods mentioned earlier in the CLEAR_FAULTS
command.
BITS
BIT
NAME
DESCRIPTION
15:8
Sample
Delay
The upper byte defines the time interval
between each sample. The sampling delay is
1.75µs + MFR_FILTER_MODE[15:8] x 250ns.
7:0
Sample
Count
The lower byte defines the number of
samples to acquire in each monitoring
sequence. The number of samples is
determined by 2^ MFR_FILTER_MODE[7:0].
Table 9. MFR_FILTER_MODE Bit
Definition
BIT FAULT/WARNING BIT NAME
15 Reserved. Read returns 0.
14 OT_WARN
13 OT_FAULT
12 IOUT_OC_WARN
11 IOUT_NC_FAULT
10 VOUT_UV_WARN
9 VOUT_UV_FAULT
8 VOUT_OV_WARN
7 Reserved. Read returns 0.
6 OFF
5 VOUT_OV_FAULT
4 IOUT_OC_FAULT
3 Reserved. Read returns 0.
2
TEMPERATURE. Set when either OT_WARN or
OT_FAULT is set.
1 CML
0
OTHER. Set when any bit (other than those
temperature related bits) in the high byte is set.
Table 10. MFR_FAULT_STATUS Bit
Definition
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

MAX8688ALETG+

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Buy MAX8688ALETG+
Manufacturer:
Maxim Integrated
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Current & Power Monitors & Regulators Digital Power-Supply Controller/Monitor
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