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HVF18C64_128_256x72G.fm - Rev. B 5/06 EN
11 ©2003 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
PLL
PLL
Notes: 1. Timing and switching specifications for the PLL listed above are critical for proper operation
of the DDR2 SDRAM Registered DIMMs. These are meant to be a subset of the parameters
for the specific device used on the module. Detailed information for this PLL is available in
JEDEC Standard JESD82.
Table 10: PLL (uses a 97U877B device)
Parameter Symbol Pins Condition Min Max Units
DC high-level input voltage
V
IH RESET# LVCMOS 0.65 × VDD –mV
DC low-level input voltage
V
IL RESET# LVCMOS – 0.35 × VDD mV
Input voltage (limits)
V
IN RESET#, CK, CK# –0.3 VDDQ + 0.3 mV
DC high-level input voltage
V
IH CK, CK# Differential Input 0.65 × VDD –mV
DC low-level input voltage
V
IL CK, CK# Differential Input – 0.35 × VDD mV
Input differential-pair cross
voltage
V
IX CK, CK# Differential Input (VDDQ/2) -
0.15
(VDDQ/2) +
0.15
V
Input differential voltage
V
ID(DC) CK, CK# Differential Input 0.3 VDDQ + 0.4 V
Input differential voltage
V
ID(AC) CK, CK# Differential Input 0.6 VDDQ + 0.4 V
Input current
I
I RESET# VI = VDDQ or VSSQ –10 10 µA
CK, CK# V
I = VDDQ or VSSQ –250 250 µA
Output disabled current
I
ODL RESET# = VSSQ; VI = VIH(AC) or
VIL(DC)
100 – µA
Static supply current
I
DDLD CK = CK# = LOW – 500 uA
Dynamic supply
I
DD N/A CK, CK# = 270 MHz, all
outputs open
(not connected to PCB)
–300mA
Input capacitance
C
IN Each input VI = VDDQ or VSSQ23pF
Table 11: PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
Parameter Symbol
0°C ≤ T
OPR
≤ +55°C
VDD = +1.8V ±0.1V
UnitsMin Max
Stabilization time
t
L– 15µs
Input clock slew rate
t
LS
I
1.0 4 V/ns
SSC modulation frequency
30 33 kHZ
SSC clock input frequency deviation
0.0 –0.50 %
PLL loop bandwidth (-3dB from unity gain)
2.0 – MHz
