Obsolete Product
X24C44
Characteristics subject to change without notice.
3 of 14
REV 1.0 6/22/00
www.xicor.com
WRDS and WREN
Internally the X24C44 contains a “write enable” latch.
This latch must be set for either writes to the RAM or
store operations to the EEPROM. The WREN instruction
sets the latch and the WRDS instruction resets the latch,
disabling both RAM writes and EEPROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
STO and STORE
Either the software STO instruction or a LOW on the
STORE input will initiate a transfer of data from RAM to
EEPROM. In order to safeguard against unwanted
store operations, the following conditions must be true:
–STO instruction issued or STORE input is LOW.
– The internal “write enable” latch must be set (WREN
instruction issued).
– The “previous recall” latch must be set (either a soft-
ware or hardware recall operation).
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
WRITE
The WRITE instruction contains the 4-bit address of the
word to be written. The write instruction is immediately
followed by the 16-bit word to be written. CE must remain
HIGH during the entire operation. CE must go LOW
before the next rising edge of SK. If CE is brought LOW
prematurely (after the instruction but before 16 bits of
data are transferred), the instruction register will be reset
and the data that was shifted-in will be written to RAM.
If CE is kept HIGH for more than 24 SK clock cycles (8-bit
instruction plus 16-bit data), the data already shifted-in
will be overwritten.
READ
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions,
I
0
of the instruction word is a “don’t care”. This provides
two advantages. In a design that ties both DI and DO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an out-
put to an input. Secondly, it allows for valid data output
during the ninth SK clock cycle.
D0, the first bit output during a read operation, is trun-
cated. That is, it is internally clocked by the falling edge
of the eighth SK clock; whereas, all succeeding bits
are clocked by the rising edge of SK (refer to Read
Cycle Diagram).
LOW POWER MODE
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby
power mode, thereby minimizing power consumption.
SLEEP
Because the X24C44 is a low power CMOS device, the
SLEEP instruction implemented on the first generation
NMOS device has been deleted. For systems convert-
ing from the X2444 to the X24C44 the software need
not be changed; the instruction will be ignored.
Table 1. Instruction Set
Notes:
X = Don't Care
A = Address
Instruction Format, I
2
I
1
I
0
Operation
WRDS (Figure 3) 1XXXX000 Reset Write Enable Latch (Disables Writes and STOREs)
STO (Figure 3) 1XXXX001 STORE
RAM Data in EEPROM
Reserved 1XXXX010 N/A
WRITE (Figure 2) 1AAAA011 Write Data into RAM Address AAAA
WREN (Figure 3) 1XXXX100 Set Write Enable Latch (Enables Writes and STORE
s)
RCL (Figure 3) 1XXXX101 Recall EEPROM Data into RAM
READ (Figure 1) 1AAAA11X Read Data from RAM Address AAAA
