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LC717A00AJ-AH

P1-P3P4-P6P7-P9P10-P12P13-P13
LC717A00AJ
www.onsemi.com
4
Table 4. I
2
C COMPATIBLE BUS TIMING CHARACTERISTICS
(V
SS
= 0 V, V
DD
= 2.6 to 5.5 V, T
A
= −40 to +105°C, Not tested at low temperature before shipment.)
Parameter
Symbol Pin Name Conditions Min Typ Max Unit Remarks
SCL Clock Frequency f
SCL
SCL − − 400 kHz
START Condition Hold Time t
HD;STA
SCL, SDA 0.6 − −
ms
SCL Clock Low Period t
LOW
SCL 1.3 − −
ms
SCL Clock High Period t
HIGH
SCL 0.6 − −
ms
Repeated START Condition
Setup Time
t
SU;STA
SCL, SDA 0.6 − −
ms
(Note 11)
Data Hold Time t
HD;DAT
SCL, SDA 0 − 0.9
ms
Data Setup Time t
SU;DAT
SCL, SDA 100 − −
ns
(Note 11)
SDA, SCL Rise/Fall Time t
r
/ t
f
SCL, SDA − − 300 ns (Note 11)
STOP Condition Setup Time t
SU;STO
SCL, SDA 0.6 − −
ms
STOP-to-START Bus Release Time t
BUF
SCL, SDA 1.3 − −
ms
(Note 11)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Design-guaranteed values (not tested before shipment).
Table 5. SPI BUS TIMING CHARACTERISTICS
(V
SS
= 0 V, V
DD
= 2.6 to 5.5 V, T
A
= −40 to +105°C, Not tested at low temperature before shipment.)
Parameter
Symbol Pin Name Conditions Min Typ Max Unit Remarks
SCK Clock Frequency f
SCK
SCK − − 5 MHz
SCK Clock Low Time t
LOW
SCK 90 − − ns (Note 12)
SCK Clock High Time t
HIGH
SCK 90 − − ns (Note 12)
Input Signal Rise/Fall Time t
r
/ t
f
nCS, SCK, SI − − 300 ns (Note 12)
nCS Setup Time t
SU;NCS
nCS, SCK 90 − − ns (Note 12)
SCK Clock Setup Time t
SU;SCK
nCS, SCK 90 − − ns (Note 12)
Data Setup Time t
SU;SI
SCK, SI 20 − − ns (Note 12)
Data Hold Time t
HD;SI
SCK, SI 30 − − ns (Note 12)
nCS Hold Time t
HD;NCS
nCS, SCK 90 − − ns (Note 12)
SCK Clock Hold Time t
HD;SCK
nCS, SCK 90 − − ns (Note 12)
nCS Standby Pulse Width t
CPH
nCS 90 − − ns (Note 12)
Output High Impedance Time
from nCS
t
CHZ
nCS, SO − − 80 ns (Note 12)
Output Data Determination Time t
v
SCK, SO − − 80 ns (Note 12)
Output Data Hold Time t
HD;SO
SCK, SO 0 − − ns (Note 12)
Output Low Impedance Time
from SCK Clock
t
CLZ
SCK, SO 0 − − ns (Note 12)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
12.Design-guaranteed values (not tested before shipment).
LC717A00AJ
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5
Power-On Reset (POR)
When power is turned on, power-on reset is enabled inside
the LSI and its state is released after a certain power-on reset
time, t
POR.
Power-on reset operation condition: Power
supply rise rate t
VDD
must be at least 1 V/ms.
Since INTOUT pin changes from “High” to “Low” at the
same time as the released of power-on reset state, it is
possible to verify the t
POR
externally.
During power-on reset state, Cin, Cref and Pout are
unknown.
Figure 1.
t
POR
t
VDD
V
POROP
UNKNOWN
VALID
t
POROP
UNKNOWN
UNKNOWN
UNKNOWN
RESET RELEASE
t
POR
VALID
RELEASERESET
V
DD
POR
(LSI Internal
Signal)
INTOUT
Cin,
Cref,
Pout
I
2
C Compatible Bus Data Timing
Figure 2.
SDA
SCL
t
HD;STA
t
LOW
t
HIGH
t
r
condition
10%
t
f
90%
10% 10%
90% 90%
t
HD;DAT
t
SU;DAT
10% 10%
10%
90%
t
SU;STA
90% 90%
t
HD;STA
90%
10%
90%
10%
90%
10%
t
SU;STO
t
BUF
90%
Repeated START
condition
START
condition
STOP
condition
START
I
2
C Compatible Bus Communication Formats
• Write format (data can be written into sequentially incremented addresses)
Figure 3.
START Slave Address Write=L Register Address (N)ACK ACK Data written to Register Address (N) ACK Data written to Register Address (N+1) ACK STOP
Slave Slave Slave
Slave
• Read format (data can be read from sequentially incremented addresses)
Figure 4.
START Slave Address Write=L Register Address (N)ACK ACK
Data read from Register Address (N)ACKRESTART Slave Address Read=H ACK Data read from Register Address (N+1) ACK Data read from Register Address (N+2) NACK STOP
Slave
Slave
Slave
Master Master
Master
LC717A00AJ
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6
I
2
C Compatible Bus Slave Address
Selection of two kinds of addresses is possible through the SA terminal.
Table 6.
SA Pin Input 7-bit Slave Address Binary Notation 8-bit Slave Address
Low 0x16
00101100b (Write) 0x2C
00101101b (Read) 0x2D
High 0x17
00101110b (Write) 0x2E
00101111b (Read) 0x2F
SPI Data Timing (SPI Mode 0 / Mode 3)
Figure 5.
nCS
SCK
SI
SO
t
SU;SI
VALID
Hi−Z
t
r
t
HD;SI
t
SU;SCK
t
SU;NCS
t
HIGH
t
LOW
t
f
t
CPH
t
HD;NCS
t
HD;SCK
t
CLZ
t
HD;SO
t
CHZ
VALID
t
V
SPI Communication Formats (Example of Mode 0)
• Write format (data can be written into sequentially incremented addresses while holding nCS = L)
Figure 6.
nCS
SCK
SI
SO
76543
2
10
Hi−Z
Register Address(N) Data written to Register Address(N) Data written to Register Address(N+1)
Write=L
76543
2
1076543
2
10
• Read format (data can be read from sequentially incremented addresses while holding nCS = L)
Figure 7.
7
Read=H
76543
2
10
Hi−Z
nCS
SCK
SI
SO
76543
2
10
76543
2
10
Register Address(N)
Data read from Register Address(N) Data read from Register Address(N+1)
P1-P3P4-P6P7-P9P10-P12P13-P13

LC717A00AJ-AH

Mfr. #:
Buy LC717A00AJ-AH
Manufacturer:
ON Semiconductor
Description:
Capacitive Touch Sensors TOUCH SENSOR 8CH 8OUT
Lifecycle:
New from this manufacturer.
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