RT9742
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Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Over-Current protection devices such as fuses and PTC
resistors (also called polyfuse or polyswitch) have slow
trip times, high on-resistance, and lack the necessary
circuitry for USB-required fault reporting.
The faster trip time of the RT9742 power distribution allows
designers to design hubs that can operate through faults.
The RT9742 provides low on-resistance and internal fault-
reporting circuitry to meet voltage regulation and fault
notification requirements.
Because the devices are also power switches, the designer
of self-powered hubs has the flexibility to turn off power to
output ports. Unlike a normal MOSFET, the devices have
controlled rise and fall times to provide the needed inrush
current limiting required for the bus-powered hub power
switch.
Supply Filter/Bypass Capacitor
A 10μF low-ESR ceramic capacitor from V
IN
to GND,
located at the device is strongly recommended to prevent
the input voltage drooping during hot-plug events. However,
higher capacitor values will further reduce the voltage droop
on the input. Furthermore, without the bypass capacitor,
an output short may cause sufficient ringing on the input
(from source lead inductance) to destroy the internal
control circuitry. The input transient must not exceed 7V
of the absolute maximum supply voltage even for a short
duration.
Output Filter Capacitor
A low-ESR 150μF aluminum electrolytic or tantalum
between VOUT and GND is strongly recommended to
meet the 330mV maximum droop requirement in the hub
V
BUS
(Per USB 2.0, output ports must have a minimum
120μF of low-ESR bulk capacitance per hub). Standard
bypass methods should be used to minimize
inductance and resistance between the bypass capacitor
and the downstream connector to reduce EMI and
decouple voltage droop caused when downstream cables
are hot-insertion transients. Ferrite beads in series with
V
BUS
, the ground line and the 0.1μF bypass capacitors at
the power connector pins are recommended for EMI and
ESD protection. The bypass capacitor itself should have
a low dissipation factor to allow decoupling at higher
frequencies.
Voltage Drop
The USB specification states a minimum port-output
voltage in two locations on the bus, 4.75V out of a Self-
Powered Hub port and 4.40V out of a Bus-Powered Hub
port. As with the Self-Powered Hub, all resistive voltage
drops for the Bus-Powered Hub must be accounted for to
guarantee voltage regulation (see Figure 7-47 of Universal
Serial Specification Revision 2.0).
The following calculation determines V
OUT(MIN)
for multi-
ple ports (N
PORTS
) ganged together through one switch (if
using one switch per port, N
PORTS
is equal to 1) :
V
OUT (MIN)
= 4.75V [ I
I
x ( 4 x R
CONN
+ 2 x R
CABLE
) ]
(0.1A x N
PORTS
x R
SWITCH
) V
PCB
Where
R
CONN
= Resistance of connector contacts
(two contacts per connector)
R
CABLE
= Resistance of upstream cable wires
(one 5V and one GND)
R
SWITCH
= Resistance of power switch
V
PCB
= PCB voltage drop
The USB specification defines the maximum resistance
per contact (R
CONN
) of the USB connector to be 30mΩ
and the drop across the PCB and switch to be 100mV.
This basically leaves two variables in the equation: the
resistance of the switch and the resistance of the cable. If
the hub consumes the maximum current (I
I
) of 500mA,
the maximum resistance of the cable is 90mΩ.
The resistance of the switch is defined as follows :
R
SWITCH
= { 4.75V 4.4V [ 0.5A x ( 4 x 30mΩ + 2 x
90mΩ) ] V
PCB
}
( 0.1A x N
PORTS
)
= (200mV V
PCB
)
( 0.1A x N
PORTS
)
RT9742
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DS9742-07 June 2017www.richtek.com
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Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Figure 1. Derating Curve of Maximum Power Dissipation
If the voltage drop across the PCB is limited to 100mV,
the maximum resistance for the switch is 250mΩ for four
ports ganged together. The RT9742, with its maximum
100mΩ on-resistance over temperature, can fit the demand
of this requirement.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
JA
, is layout dependent. For
SOT-23-3 package, the thermal resistance, θ
JA
, is
243.3°C/W on a standard JEDEC 51-7 four-layer thermal
test board. For TSOT-23-5 package, the thermal
resistance, θ
JA
, is 203°C/W on a standard JEDEC 51-7
four-layer thermal test board. For TSOT-23-5 (FC) package,
the thermal resistance, θ
JA
, is 126.5°C/W on a standard
JEDEC 51-7 four-layer thermal test board. The maximum
power dissipation at T
A
= 25°C can be calculated by the
following formula :
P
D(MAX)
= (125°C 25°C) / (243.3°C/W) = 0.41W for
SOT-23-3 package
P
D(MAX)
= (125°C 25°C) / (203°C/W) = 0.49W for
TSOT-23-5 package
P
D(MAX)
= (125°C 25°C) / (126.5°C/W) = 0.79W for
TSOT-23-5 (FC) package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Layout Consideration
In order to meet the voltage drop, droop, and EMI
requirements, careful PCB layout is necessary. The
following guidelines must be followed :
Locate the ceramic bypass capacitors as close as
possible to the VIN pins of the RT9742.
Place a ground plane under all circuitry to lower both
resistance and inductance and improve DC and transient
performance (Use a separate ground and power plans if
possible).
Keep all V
BUS
traces as short as possible and use at
least 50-mil, 2 ounce copper for all V
BUS
traces.
Avoid vias as much as possible. If vias are necessary,
make them as large as feasible.
Place cuts in the ground plane between ports to help
reduce the coupling of transients between ports.
Locate the output capacitor and ferrite beads as close
to the USB connectors as possible to lower impedance
(mainly inductance) between the port and the capacitor
and improve transient load performance.
Locate the RT9742 as close as possible to the output
port to limit switching noise.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB
SOT-23-3
TSOT-23-5
TSOT-23-5 (FC)
RT9742
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DS9742-07 June 2017 www.richtek.com
©
Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Figure 2. PCB Layout Guide
GND
EN
GND_BUS
V
IN
V
OUT
V
BUS
V
IN
FLG
The input capacitor should
be placed as close as
possible to the IC.
The input capacitor should be
placed as close as possible to
the IC.
GND
VIN VOUT
+
+
GND_BUS
V
BUS
+

RT9742DGJ5

Mfr. #:
Manufacturer:
Description:
IC USB POWER SWITCH TSOT23-5
Lifecycle:
New from this manufacturer.
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