6
LT1725
1725fa
UU
U
PI FU CTIO S
PGND (Pin 1): The power ground pin carries the GATE
node discharge current. This is typically a current spike of
several hundred mA with a duration of tens of nanosec-
onds. It should be connected directly to a good quality
ground plane.
I
SENSE
(Pin 2): Pin to measure switch current with exter-
nal sense resistor. The sense resistor should be of a
noninductive construction as high speed performance is
essential. Proper grounding technique is also required to
avoid distortion of the high speed current waveform. A
preset internal limit of nominally 250mV at this pin effects
a switch current limit.
SFST (Pin 3): Pin for optional external capacitor to effect
soft-start function. See Applications Information for details.
R
OCMP
(Pin 4): Input pin for optional external load compen-
sation resistor. Use of this pin allows nominal compensa-
tion for nonzero output impedance in the power transformer
secondary circuit, including secondary winding impedance,
output Schottky diode impedance and output capacitor
ESR. In less demanding applications, this resistor is not
needed. See Applications Information for more details.
R
CMPC
(Pin 5): Pin for external filter capacitor for optional
load compensation function. A common 0.1µF ceramic
capacitor will suffice for most applications. See Applica-
tions Information for further details.
OSCAP (Pin 6): Pin for external timing capacitor to set
oscillator switching frequency. See Applications Informa-
tion for details.
V
C
(pin 7): This is the control voltage pin which is the
output of the feedback amplifier and the input of the
current comparator. Frequency compensation of the
overall loop is effected in most cases by placing a capaci-
tor between this node and ground.
FB (Pin 8): Input pin for external “feedback” resistor
divider. The ratio of this divider, times the internal
bandgap (V
BG
) reference, times the effective output-to-
third winding transformer turns ratio is the primary deter-
minant of the output voltage. The Thevenin equivalent
resistance of the feedback divider should be roughly 3k.
See Applications Information for more details.
3V
OUT
(Pin 9): Output pin for nominal 3V reference. This
facilitates various user applications. This node is internally
current limited for protection and is intended to drive
either moderate capacitive loads of several hundred pF or
less, or, very large capacitive loads of 0.1µF or more. See
Applications Information for more details.
UVLO (Pin 10): This pin allows the use of an optional
external resistor divider to set an undervoltage lockout
based upon V
IN
(not V
CC
) level. (Note: If the V
CC
voltage is
sufficient to allow the part to start up, but the UVLO pin is
held below its threshold, output switching action will be
disabled, but the part will draw its normal quiescent
current from V
CC
. This typically causes a benign relaxation
oscillation action on the V
CC
pin in the conventional
“trickle-charge” bootstrapped configuration.)
The bias current on this pin is a function of the state of the
UVLO comparator; as the threshold is exceeded, the bias
current increases. This creates a hysteresis band equal to
the change in bias current times the Thevenin impedance
of the user’s resistive divider. The user may thereby adjust
the impedance of the UVLO divider to achieve a desired
degree of hysteresis. A 100pF capacitor to ground is
recommended on this pin. See Applications Information
for details.
SGND (Pin 11): The signal ground pin is a clean ground.
The internal reference, oscillator and feedback amplifier
are referred to it. Keep the ground path connection to the
FB pin, OSCAP capacitor and the V
C
compensation capaci-
tor free of large ground currents.
MINENAB (Pin 12): Pin for external programming resistor
to set minimum enable time. See Applications Information
for details.
