LT1725IGN#PBF Datasheet LT1725CS#TRPBF, LT1725CGN#TRPBF, LT1725IS#TRPBF | P16-P18

LT1725

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amplified. If severe enough, this can cause erratic opera-

tion. For example, assume 3nH of parasitic inductance

(equivalent to about 0.1 inch of wire in free space) is in series

with an ideal 0.025Ω sense resistor. A “zero” will be formed

at f = R/(2πL), or 1.3MHz. Above this frequency the sense

resistor will behave like an inductor.

Several techniques can be used to tame this potential

parasitic inductance problem. First, any resistor used for

current sensing purposes must be of an inherently non-

inductive construction. Mounting this resistor directly

above an unbroken ground plane and minimizing its

ground side connection will serve to absolutely minimize

parasitic inductance. In the case of low valued sense

resistors, these may be implemented as a parallel combi-

nation of several resistors for the thermal considerations

cited above. The parallel combination will help to lower the

parasitic inductance. Finally, it may be necessary to place

a “pole” between the current sense resistor and the

LT1725 I

SENSE

pin to undo the action of the inductive zero

(see Figure 5). A value of 51Ω is suggested for the resistor,

while the capacitor is selected empirically for the particular

application and layout. Using good high frequency mea-

surement techniques, the I

SENSE

pin waveform may be

observed directly with an oscilloscope while the capacitor

value is varied.

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GATE

PARASITIC

INDUCTANCE

COMP

SENSE

1725 F05

51Ω

PGNDSGND

SENSE

f =

SENSE

2πL

SENSE RESISTOR ZERO AT:

f =

2π(51Ω)C

COMP

COMPENSATING POLE AT:

COMP

SENSE

(51Ω)

FOR CANCELLATION:

Figure 5

SOFT-START FUNCTION

The LT1725 contains an optional soft-start function that is

enabled by connecting an explicit external capacitor be-

tween the SFST pin and ground. Internal circuitry prevents

the control voltage at the V

pin from exceeding that on the

SFST pin.

The soft-start function is enagaged whenever V

power

is removed, or as a result of either undervoltage lockout

or thermal (overtemperature) shutdown. The SFST node

is then discharged to roughly a V

above ground.

(Remember that the V

pin control node switching thresh-

old is deliberately set at a V

plus

several hundred

millivolts.) When this condition is removed, a nominal

40µA current acts to charge up the SFST node towards

roughly 3V. So, for example, a 0.1µF soft-start capacitor

will place a 0.4V/ms limit on the ramp rate at the V

node.

UVLO PIN FUNCTION

The UVLO pin effects an undervoltage lockout function

with at threshold of roughly 1.25V. An external resistor

divider between the input supply and ground can then be

used to achieve a user-programmable undervoltage lock-

out (see Figure 6a).

An additional feature of this pin is that there is a change in

the input bias current at this pin as a function of the state

of the internal UVLO comparator. As the pin is brought

above the UVLO threshold, the bias current sourced by the

part increases. This positive feedback effects a hysteresis

band for reliable switching action. Note that the size of the

hysteresis is proportional to the Thevenin impedance of

the external UVLO resistor divider network, which makes

it user programmable. As a rough rule of thumb, each 4k

or so of impedance generates about 1% of hysteresis.

(This is based on roughly 1.25V for the threshold and 3µA

for the bias current shift.)

Even in good quality ground plane layouts, it is common

for the switching node (MOSFET drain) to couple to the

UVLO pin with a stray capacitance of several

thousandths

of a pF. To ensure proper UVLO action, a 100pF capacitor

is recommended from this pin to ground as shown in

Figure 6b. This will typically reduce the coupled noise to

a few millivolts. The UVLO filter capacitor should not be

made much larger than a few hundred pF, however, as the

hysteresis action will become too slow. In cases where

further filtering is required, e.g., to attenuate high speed

supply ripple, the topology in Figure 6c is recommended.

Resistor R1 has been split into two equal parts. This

provides a node for effecting capacitor filtering of high

LT1725

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(6a) “Standard” UVLO

Divider Topology

UVLO

(6b) Filter Capacitor

Directly On UVLO Node

UVLO

100pF

(6c) Recommended Topology to

Filter High Frequency Ripple

UVLO

R1/2

1725 F06

100pF

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Figure 6

speed supply ripple, while leaving the UVLO pin node

impedance relatively unchanged at high frequency.

INTERNAL WIDE HYSTERESIS

UNDERVOLTAGE LOCKOUT

The LT1725 is designed to implement isolated DC/DC

converters operating from input voltages of typically 48V

or more. The standard operating topology utilizes a third

transformer winding on the primary side that provides

both feedback information and local power for the LT1725

via its V

pin. However, this arrangement is not inherently

self-starting. Start-up is effected by the use of an external

“trickle-charge” resistor and the presence of an internal

wide hysteresis undervoltage lockout circuit that monitors

pin voltage (see Figure 7). Operation is as follows:

“Trickle charge” resistor R1 is connected to V

and

supplies a small current, typically on the order of a single

mA, to charge C1. At first, the LT1725 is off and draws only

its start-up current. After some time, the voltage on C1

) reaches the V

turn-on threshold. The LT1725 then

turns on abruptly and draws its normal supply current.

Switching action commences at the GATE pin and the

MOSFET begins to deliver power. The voltage on C1

begins to decline as the LT1725 draws its normal supply

current, which greatly exceeds that delivered by R1. After

some time, typically tens of milliseconds, the output

voltage approaches its desired value. By this time, the

third transformer winding is providing virtually all the

supply current required by the LT1725.

One potential design pitfall is undersizing the value of

capacitor C1. In this case, the normal supply current

VCC

1725 F07

VCC

THRESHOLD

GATE

LT1725 GATE

PGND SGND

Figure 7

drawn by the LT1725 will discharge C1 too rapidly; before

the third winding drive becomes effective, the V

turn-off

threshold will be reached. The LT1725 turns off, and the

node begins to charge via R1 back up to the turn-on

threshold. Depending upon the particular situation, this

may result in either several on-off cycles before proper

operation is reached, or, permanent relaxation oscillation

at the V

node.

Component selection is as follows:

Resistor R1 should be selected to yield a worst-case

minimum charging current greater than the maximum

rated LT1725 start-up current, and a worst-case maxi-

mum charging current less than the minimum rated

LT1725 supply current.

LT1725

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Capacitor C1 should then be made large enough to avoid

the relaxation oscillatory behavior described above. This

is complicated to determine theoretically as it depends on

the particulars of the secondary circuit and load behavior.

Empirical testing is recommended. (Use of the optional

soft-start function will lengthen the power-up timing and

require a correspondingly larger value for C1.)

A further note—certain users may wish to utilize the

general functionality of the LT1725, but may have an

available input voltage significantly lower than, say, 48V.

If this input voltage is within the allowable V

range, i.e.,

perhaps 20V maximum, the internal wide hysteresis range

UVLO function becomes counterproductive. In such cases

it is simply better to operate the LT1725 directly from the

available DC input supply. The LT1737 is identical to the

LT1725, with the exception that it lacks the internal wide

hysteresis UVLO function. It is therefore designed to

operate directly from DC input supplies in the range of

4.5V to 20V. See the LT1737 data sheet for further

information.

FREQUENCY COMPENSATION

Loop frequency compensation is performed by connect-

ing a capacitor from the output of the error amplifier (V

pin) to ground. An additional series resistor, often re-

quired in traditional current mode switcher controllers, is

usually not required and can even prove detrimental. The

phase margin improvement traditionally offered by this

extra resistor will usually be already accomplished by the

nonzero secondary circuit impedance, which adds a “zero”

to the loop response.

In further contrast to traditional current mode switchers,

pin ripple is generally not an issue with the LT1725. The

dynamic nature of the clamped feedback amplifier forms

an effective track/hold type response, whereby the V

voltage changes during the flyback pulse, but is then “held”

during the subsequent “switch on” portion of the next

cycle. This action naturally holds the V

voltage stable

during the current comparator sense action (current mode

switching).

OUTPUT VOLTAGE ERROR SOURCES

Conventional nonisolated switching power supply ICs

typically have only two substantial sources of output

voltage error: the internal or external resistor divider

network that connects to V

OUT

and the internal IC refer-

ence. The LT1725, which senses the output voltage in both

a dynamic and an isolated manner, exhibits additional

potential error sources to contend with. Some of these

errors are proportional to output voltage, others are fixed

in an absolute millivolt sense. Here is a list of possible

error sources and their effective contribution.

Internal Voltage Reference

The internal bandgap voltage reference is, of course,

imperfect. Its error, both at 25°C and over temperature is

already included in the specifications.

User Programming Resistors

Output voltage is controlled by the user-supplied feedback

resistor divider ratio. To the extent that the resistor ratio

differs from the ideal value, the output voltage will be

proportionally affected. Highest accuracy systems will

demand 1% components.

Schottky Diode Drop

The LT1725 senses the output voltage from the trans-

former primary side during the flyback portion of the cycle.

This sensed voltage therefore includes the forward drop,

, of the rectifier (usually a Schottky diode). The nominal

of this diode should therefore be included in feedback

resistor divider calculations. Lot to lot and ambient tem-

perature variations will show up as output voltage shift/

drift.

Secondary Leakage Inductance

Leakage inductance on the transformer secondary re-

duces the effective secondary-to-third winding turns ratio

) from its ideal value. This will increase the output

voltage target by a similar percentage. To the extent that

secondary leakage inductance is constant from part to

part, this can be accommodated by adjusting the feedback

resistor ratio.

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