USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
DS00001714A-page 10 2014 Microchip Technology Inc.
Chapter 3 Ball Descriptions
Figure 3.1 30-WLCSP Pin Assignments
SUSPEND/
IRQ_N/
INT_N
HUB_CONN
REFSEL0
SDA/
SMBDATA
SPI_CE_N
Top of USB3613 Package
A
B
C
D
E
12345
6
STRB0
RESET_N
SCL/
SMBCLK
SPI_CLK
SPI_DI
DATA0
GND
RBIAS
SPI_DO/
SPI_SPD_SEL
PRTCTLA
REFCLK
VDD33
GND
CHRGDET0
CHRGDET1
VDDCORE
REG
VBAT
DM1
DM2
DATA3
VDDCR12
DP1
DP2
STRB3
REFSEL1
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
2014 Microchip Technology Inc. DS00001714A-page 11
3.1 Ball Descriptions
This section provides a detailed description of each ball. The signals are arranged in functional groups
according to their associated interface.
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal
is at a low voltage level. For example, RESET_N indicates that the reset signal is active low. When
“_N” is not present after the signal name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working
with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a
signal is active, independent of whether that level is represented by a high or low voltage. The term
negate, or negation, indicates that a signal is inactive.
Note: The buffer type for each signal is indicated in the BUFFER TYPE column of Table 3.1. A
description of the buffer types is provided in Section 3.3.
Table 3.1 Ball Descriptions
NUM
BALLS NAME SYMBOL
BUFFER
TYPE DESCRIPTION
USB/HSIC INTERFACES
1
Upstream
HSIC Data
(Flex Port 0)
DATA0 HSIC Upstream HSIC Port 0 DATA signal.
Note: The upstream Port 0 signals can be
optionally swapped with the
downstream Port 1 signals.
1
Upstream
HSIC Strobe
(Flex Port 0)
STRB0 HSIC Upstream HSIC Port 0 STROBE signal.
Note: The upstream Port 0 signals can be
optionally swapped with the
downstream Port 1 signals.
1
Downstream
USB D+
(Swap Port 1)
DP1 AIO Downstream USB Port 1 D+ data signal.
Note: The downstream Port 1 signals can be
optionally swapped with the upstream
Port 0 signals.
1
Downstream
USB D-
(Swap Port 1)
DM1 AIO Downstream USB Port 1 D- data signal.
Note: The downstream Port 1 signals can be
optionally swapped with the upstream
Port 0 signals.
1
Downstream
USB D+
(Port 2)
DP2 AIO Downstream USB Port 2 D+ data signal.
1
Downstream
USB D-
(Port 2)
DM2 AIO Downstream USB Port 2 D- data signal.
1
Downstream
HSIC Data
(Port 3)
DATA3 HSIC Downstream HSIC Port 3 DATA signal.
1
Downstream
HSIC Strobe
(Port 3)
STRB3 HSIC Downstream HSIC Port 3 STROBE signal.
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
DS00001714A-page 12 2014 Microchip Technology Inc.
I
2
C/SMBUS INTERFACE
1
I
2
C Serial
Clock Input
SCL I_SMB I
2
C serial clock input.
SMBus Clock SMBCLK I_SMB SMBus serial clock input.
1
I
2
C Serial
Data
SDA IS/OD8 I
2
C bidirectional serial data.
SMBus Serial
Data
SMBDATA IS/OD8 SMBus bidirectional serial data.
SPI MASTER INTERFACE
1
SPI Chip
Enable
Output
SPI_CE_N O12 Active-low SPI chip enable output.
Note: If the SPI is enabled, this pin will be
driven high in powerdown states.
1
SPI Clock
Output
SPI_CLK O12 SPI clock output
1
SPI Data
Output
SPI_DO O12 SPI data output
SPI Speed
Select
Configuration
Strap
SPI_SPD_SEL
IS
(PD)
This strap is used to select the speed of the SPI.
0 = 30MHz (default)
1 = 60MHz
Note: If the latched value on reset is 1, this pin
is tri-stated when the chip is in the
suspend state. If the latched value on
reset is 0, this pin is driven low during a
suspend state.
See Note 3.2 for more information on
configuration straps.
1
SPI Data
Input
SPI_DI IS
(PD)
SPI data input
MISC.
1
Reference
Clock Input
REFCLK ICLK This signal is the reference clock input. The clock
input frequency is configured via REFSEL[1:0].
Refer to Section 8.4, "Reference Clock," on
page 41 for additional information.
1
Reference
Clock Select
0 Input
REFSEL0 IS This signal, combined with REFSEL1, selects the
reference clock input frequency. The reference
select input must be set to correspond to the
frequency applied to the REFCLK input. Refer to
Section 8.4, "Reference Clock," on page 41 for
additional information.
Table 3.1 Ball Descriptions (continued)
NUM
BALLS NAME SYMBOL
BUFFER
TYPE DESCRIPTION

USB3613I-1080XY-TR

Mfr. #:
Manufacturer:
Microchip Technology
Description:
USB Interface IC USB 2.0 Hi-Spd 3-pt Hub Cntlr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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