©2013 Integrated Device Technology, Inc.
1
OCTOBER 2013
DSC-5622/7
Functional Block Diagram
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Fully asynchronous operation from either port
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Separate byte controls for multiplexed bus and bus
matching compatibility
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Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
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LVTTL-compatible, single 3.3V (±150mV) power supply for
core
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LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
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Available in a 128-pin Thin Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
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Industrial temperature range (–40°C to +85°C) is available
for selected speeds
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Green parts available, see ordering information
Features
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True Dual-Port memory cells which allow simultaneous
access of the same memory location
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High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12ns (max.)
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Dual chip enables allow for depth expansion without
external logic
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IDT70V631 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
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M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
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Busy and Interrupt Flags
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On-chip port arbitration logic
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Full on-chip hardware support of semaphore signaling
between ports
HIGH-SPEED 3.3V 256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
IDT70V631S
NOTES:
1. BUSY is an input as a Slave (M/S=V
IL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
CE
0R
R/
W
R
CE
1R
LB
R
UB
R
256K x 18
MEMORY
ARRAY
Address
Decoder
A
17R
A
0R
Address
Decoder
CE
0L
R/
W
L
CE
1L
LB
L
UB
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
I/O
0L
- I/O
17L
I/O
0R
-I/O
17R
Din_L
ADDR_L
Din_R
ADDR_R
OE
R
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM
L
INT
L
BUSY
L
M/S
R/W
L
OE
L
R/W
R
OE
R
BUSY
R
SEM
R
INT
R
CE
0L
CE
1L
CE
0R
CE
1R
TMS
TCK
TRST
TDI
TDO
JTAG
5622 drw 01
A
17L
A
0L