5
IDT70V631S
High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Names
NOTES:
1. V
DD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/O
X.
2. OPT
X selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
Left Port Right Port Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
17L
A
0R
- A
17R
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
UB
L
UB
R
Upper Byte Select
LB
L
LB
R
Lower Byte Select
V
DD Q L
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(1)
OPT
L
OPT
R
Option for selecting V
DDQX
(1,2)
M/S Master or Slave Select
V
DD
Power (3.3V)
(1 )
V
SS
Ground (0V)
TDI Test Data Input
TDO Test Data Output
TCK Test Logic Clock (10MHz)
TMS Test Mode Select
TRST
Reset (Initialize TAP Controller)
5622 tbl 01