®
AS7C4096A
2/21/06, v 1.2 Alliance Semiconductor P. 6 of 10
Write waveform 2 (CE controlled)
9
AC test conditions
Notes
1During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
2 For test conditions, see AC Test Conditions.
3t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
4 This parameter is guaranteed, but not tested.
5WE
is HIGH for read cycle.
6CE
and OE are LOW for read cycle.
7 Address valid prior to or coincident with CE
transition Low.
8 All read cycle timings are referenced from the last valid address to the first transitioning address.
9 All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
t
AW
Address
CE
WE
t
CW
t
DW
t
DH
t
AH
t
WC
t
AS
Data valid
D
IN
t
WR
t
WP
255
Ω
C
10
480
Ω
D
OUT
GND
+5.0V
Figure B: 5.0V Output load
- Output load: see Figure B.
- Input pulse level: GND to V
CC
- 0.5V. See Figures A and B.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
168
Ω
Thevenin equivalent:
D
OUT
+1.728V
10%
90%
10%
90%
GND
V
CC
- 0.5V
Figure A: Input pulse
2 ns
