ZXFV4089N8TC Datasheet ZXFV4089N8TA, ZXFV4089N8TC | P7-P9

ZXFV4089

Issue 4 - December 2008 7 www.zetex.com

ZXFV4089 detailed operating notes

Introduction

This device provides an uncommitted video feed-back amplifier together with a sample-hold

system to allow restoration or level-shifting of the input waveform to a controlled DC level.

The connection diagram, Figure 1 shows a typical video signal application. No output termination

is shown in the diagram, but if desired the output can drive a 75⍀ cable via a 75⍀ series

terminating resistor.

Amplifier configuration

The main amplifier uses current feedback in a non-inverting configuration. Two external resistors

are required to set the gain.

An external reference, V

REF

, normally ground, is used to set the new DC level of the video signal.

The input video signal is applied via an external input AC coupling capacitor, which is used to

store a DC control level when the sample-hold switch is open. Typically an external sampling

pulse (active low) is applied to the HOLD input. During this pulse, the sample-hold switch is

closed. This completes the DC feedback loop and the stored level is driven towards a new value.

At the end of the sampling pulse, the switch opens again and the DC level remains close to the

new established value until the next sample pulse. The sample-hold charging current is limited

to 300µA. Therefore the convergence towards the steady condition is typically slow, but after

several HOLD pulse cycles, the DC level settles closely to the Reference level at the V

REF

input.

The sample-hold loop contains the video amplifier within its path, and also includes an additional

sample-hold sense amplifier that compares V

REF

with the output voltage using an internal low-

pass filter. In the high state, the switch is open and the average DC level remains fixed apart from

a small drift due to the input bias current of the amplifier and switch leakage (see below).

DC restoration

The HOLD input is a TTL compatible signal that is buffered and controls the sample-hold switch.

A logic LOW state closes the switch and so enables the feedback control loop to set the output

level equal to V

REF

(usually ground). The level of DC shift is maintained when the logic control

returns to the HIGH state and the switch opens. In this way the whole waveform is conditionally

level shifted, or 'restored' to the new DC level. Figure 2 shows the response of the circuit to a

stationary or very slowly varying waveform with an initial voltage offset difference between V+

and V

REF

, applied to the input coupling capacitor, when the HOLD input is cycled with a repetitive

pulse waveform. When the HOLD input is at a logic LOW level, the signal input V+ is driven

towards V

REF

. After a number of cycles, the waveform settles to the DC stabilised value. The

waveform is unaffected during the logic HIGH interval of the HOLD input.

Figure 2 Response to slow input signal

ZXFV4089

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Figure 3 shows a portion of a typical video waveform, where the sample pulse is synchronised to

fall within the back porch interval. This can for example be achieved using the Zetex ZXFV4583

sync separator to derive the pulse as in the evaluation circuit described in the data sheet for that

part. Again, during the logic LOW period of the HOLD input, the waveform is driven towards VREF.

Eventually, after a few line scans, the video waveform is stabilised with the back porch level equal

to V

REF

and this condition is maintained despite any small changes in the input waveform.

In the video application, the HOLD input state will be HIGH during the picture line sweep and a

negative-going sampling pulse of typically 1.2µs duration will be applied during a central portion

of the back porch interval, so that the back porch or 'Black' level is clamped to V

REF

(typically

ground).

Figure 3 Response to typical video signal

If desired, by changing the external pulse timing the signal may be restored such that the sync tip

voltage is clamped to V

REF

instead of the back porch.

In either case, for each line scan, this gives a brightness level consistent with that of the original

camera signal, despite the AC coupling. The value of the coupling capacitor affects two main

characteristics of the circuit:

1. DC level acquisition change

2. DC level droop

DC level acquisition change

In the restore mode the available charging current, together with the capacitor value, determines

the maximum DC voltage correction which can be applied at each sample. For a charging current

limit of 300µA applied for 1.2µs, the charge injected is:

Qmax = 300µA x 1.2µs = 360pC

Then the maximum voltage shift correction is:

Vmax = Qmax/C = 360pC / 0.01µF

= 36mV

ZXFV4089

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DC level droop

In the hold state, a small voltage drift is caused by leakage from the sample-hold circuit and bias

current from the main amplifier charging or discharging the coupling capacitor.

The drift rate is equal to the bias/leakage current of up to about 1µA divided by the coupling

capacitor value. For a coupling capacitor of 0.01µF the drift rate is then up to ±100µV/µs.

For a typical video line scan the switch remains open for the rest of the scan duration, or about

62µs. The drift at the end of the line scan has therefore accumulated to about 6.2mV.

This is acceptable for most applications, but if desired it can be reduced by increasing the value

of the coupling capacitor. This will result in a proportionately smaller value of the maximum

available correction voltage at each scan as described above. Normally, once settled, the video

system requires only a very small correction at each scan, so this will not present any problem.

Supply filtering and printed circuit layout

In the applied circuit, the power filtering and printed layout design needs special attention as is

appropriate for a high-speed analog circuit. For each supply lead, use a leadless ceramic chip

capacitor placed very close to the device power pin. A value of 0.1µF is recommended. In addition,

a larger value capacitor, which should be ceramic or solid tantalum construction, with a value of

1 to 10µF, is also recommended for connection to each supply fairly close to the device. The

layout naturally requires some short interconnections on the component side (top copper layer)

and a continuous ground plane should be provided on another layer with plated via holes

providing low inductance ground connections for the device and other components. The

amplifier frequency response is affected to some extent by stray capacitance at the inverting input

at pin 1. This effect can be minimised by providing a small cut-out area in the ground plane and

other layers around pin 1, though this may not always be necessary for the application.

Further Applications Information

The ZXFV4089 is a high speed device requiring the appropriate care in the layout of the

application printed circuit board. A continuous ground plane construction is preferred. Suitable

power supply decoupling suggested includes a 100nF leadless ceramic capacitor close to the

power supply connections at pin 8 and pin 6.

As stated earlier the main video amplifier of the ZXFV4089 is a current feedback amplifier.

Compared to a voltage-feedback amplifier, current feedback provides better bandwidths at higher

gains and also much faster slew rates. To optimize performance from a current feedback amplifier

choice of feedback resistor is very important. In this case, typically the device will be used with a

voltage gain of two, using two resistors of 1k⍀ as in Figure 1. Stray capacitance at the inverting

input node of this circuit can affect frequency and pulse response, so the printed circuit layout

should take account of this. Place the feedback resistors as close as possible to the inverting input

pin and minimize the printed metal connected to this pin.

Common-mode input range

The signal input voltage range is determined partly by the common-mode input range of the main

amplifier. The amplifier configuration is non-inverting, and so the inverting input will follow the

signal input voltage. It is also necessary to observe the maximum limit on the value of V

REF

(±2V)

which is less than the amplifier input voltage range. Therefore the input range of the system is

limited to this value. In addition the restore amplifier voltage input range is restricted to a similar

value.

P1-P3 P4-P6 P7-P9 P10-P12

ZXFV4089N8TC

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ZXFV4089N8TC

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