Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
202857D • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 29, 2017 1
DATA SHEET
SKY13489-001: 0.7 to 2.7 GHz SPDT High Power Switch
(Single Bit Control) in a WLCSP Package
Applications
LTE TDD/FDD transmit
GSM transmit
Embedded modules
Features
Broadband frequency range: 0.7 to 2.7 GHz
Low insertion loss: 0.3 dB @ 2.7 GHz
High isolation: 22 dB up to 2.7 GHz
No external DC blocking capacitors required
Single GPIO control line with V
DD voltage regulator:
V
CTL = 1.35 to 3.00 V
V
DD = 2.45 to 4.80 V
Small, 6-bump WLCSP, 217 μm diameter, 400 μm pitch
(1.135 x 0.735 x 0.400 mm) package
(MSL1, 260 °C per JEDEC J-STD-020)
Skyworks Green
TM
products are compliant with
all applicable legislation and are halogen-free.
For additional information, refer to Skyworks
Definition of Green
TM
, document number
SQ04–0074.
202857-002
Pin A1 Indicator
A
3
2
1
B
V1
RF1
GND
ANT
VDD
RF2
Figure 2. SKY13489-001 Pinout
(Top View, Bumps Facing Down)
RF1
RF2
ANT
VDD V1
Logic and Supply
202857-001
Figure 1. SKY13489-001 Block Diagram
Description
The SKY13489-001 is a single-pole, double-throw (SPDT)
LTE/WCDMA/GSM transmit switch. Switching is controlled by an
integrated GPIO interface with a single control pin. Depending on
the logic voltage level applied to the control pin, the antenna port
is connected to one of the switched RF outputs (RF1 or RF2)
through a low insertion loss path, while the path between the
antenna port and the other RF port is in a high isolation state.
No external DC blocking capacitors are required as long as no DC
voltage is applied on any RF path.
The SKY13489-001 is provided in a compact 6-bump,
1.135 x 0.735 x 0.400 mm Wafer Level Chip Scale Package
(WLCSP) that meets requirements for board-level assembly.
Bump diameters are 217 microns with a minimum bump pitch of
400 microns.
A functional block diagram is shown in Figure 1. The pin
configuration and package are shown in Figure 2. Signal pin
assignments and functional pin descriptions are provided in
Table 1.