Document #: 38-07006 Rev. *G Page 3 of 10
Functional Description
The CY22050 is the next-generation programmable FTG
(frequency timing generator) for use in networking,
telecommunication, datacom, and other general-purpose
applications. The CY22050 offers up to six configurable outputs
in a 16-pin TSSOP, running off a 3.3V power supply. The on-chip
reference oscillator is designed to run off an 8–30-MHz crystal,
or a 1–133-MHz external clock signal.
The CY22050 has a single PLL driving 6 programmable output
clocks. The output clocks are derived from the PLL or the
reference frequency (REF). Output post dividers are available for
either. Four of the outputs can be set as 3.3V or 2.5V, for use in
a wide variety of portable and low-power applications.
The CY220501 is the CY22050 with NiPdAu lead finish.
Field Programming the CY22050F
The CY22050 is programmed at the package level, that is, in a
programmer socket, prior to installation on a PCB. The CY22050
is flash-technology based, so the parts can be reprogrammed up
to 100 times. This allows for fast and easy design changes and
product updates, and eliminates any issues with old and
out-of-date inventory.
Samples and small prototype quantities can be programmed on
the CY3672 programmer. Cypress’s value-added distribution
partners and third-party programming systems from BP Micro-
systems, HiLo Systems, and others are available for
large-production quantities.
CyberClocks™ Software
CyberClocks is an easy-to-use software application that allows
the user to custom-configure the CY22050. Within CyberClocks,
select the CyClocksRT™ tool. Users can specify the REF, PLL
frequency, output frequencies and/or post-dividers, and different
functional options. CyClocksRT outputs an industry-standard
JEDEC file used for programming the CY22050.
CyClocksRT can be downloaded free of charge from the
Cypress website at http://www.cypress.com. Install and run it on
any PC running the Windows operating system.
CY3672 Development Kit
The Cypress CY3672 Development Kit comes complete with
everything needed to design with the CY22050 and program
samples and small prototype quantities. The kit comes with the
latest version of CyClocksRT and a small portable programmer
that connects to a PC for on-the-fly programming of custom
frequencies.
The JEDEC file output of CyClocksRT can be downloaded to the
portable programmer for small-volume programming, or for use
with a production programming system for larger volumes.
Applications
Controlling Jitter
Jitter is defined in many ways, including: phase noise, long-term
jitter, cycle-to-cycle jitter, period jitter, absolute jitter, and deter-
ministic jitter. These jitter terms are usually given in terms of rms,
peak-to-peak, or in the case of phase noise dBC/Hz with respect
to the fundamental frequency. Actual jitter is dependent on XIN
jitter and edge rate, number of active outputs, output
frequencies, V
DDL
(2.5V or 3.3V), temperature, and output load.
Power supply noise and clock output loading are two major
system sources of clock jitter. Power supply noise can be
mitigated by proper power supply decoupling (0.1-μF ceramic
cap) of the clock and ensuring a low-impedance ground to the
chip. Reducing capacitive clock output loading to a minimum
lowers current spikes on the clock edges and thus reduces jitter.
Reducing the total number of active outputs also reduce jitter in
a linear fashion. However, it is better to use two outputs to drive
two loads than one output to drive two loads.
The rate and magnitude that the PLL corrects the VCO frequency
is directly related to jitter performance. If the rate is too slow, then
long term jitter and phase noise is poor. Therefore, to improve
long-term jitter and phase noise, reducing Q to a minimum is
advisable. This technique increases the speed of the phase
frequency detector, which in turn drives the input voltage of the
VCO. In a similar manner, increasing P until the VCO is near its
maximum rated speed also decreases long term jitter and phase
noise. For example: input reference of 12 MHz; desired output
frequency of 33.3 MHz. One might arrive at the following
solution: Set Q = 3, P = 25, Post Div = 3. However, the best jitter
results are Q = 2, P = 50, Post Div = 9.
For additional information, refer to the application note, “Jitter in
PLL-based Systems: Causes, Effects, and Solutions,” available
at http://www.cypress.com (click on “Application Notes”), or
contact your local Cypress Field Applications Engineer.
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