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CY22050ZXC-134T

P1-P3P4-P6P7-P9P10-P10
CY22050,
CY220501
Document #: 38-07006 Rev. *G Page 4 of 10
CY22050 Frequency Calculation
The CY22050 is an extremely flexible clock generator with up to
six individual outputs, generated from an integrated PLL.
There are four variables used to determine the final output
frequency. They are: the input REF, the P and Q dividers, and
the post divider. The three basic formulas for determining the
final output frequency of a CY22150-based design are:
■ CLK = ((REF * P)/Q)/Post Divider
■ CLK = REF/Post Divider
■ CLK = REF
The basic PLL block diagram is shown in Figure 2. Each of the
six clock outputs has a total of seven output options available to
it. There are six post divider options: /2 (two of these), /3, /4,
/DIV1N, and DIV2N. DIV1N and DIV2N are separately calculated
and can be independent of each other. The post divider options
can be applied to the calculated PLL frequency or to the REF
directly.
In addition to the six post divider options, the seventh option
bypasses the PLL and passes the REF directly to the crosspoint
switch matrix.
Clock Output Settings: Crosspoint Switch
Matrix
Each of the six clock outputs can come from any of seven unique
frequency sources. The crosspoint switch matrix defines which
source is attached to each individual clock output. Although it
may seem that there are an unlimited number of divider options,
there are several rules that must be taken into account when
selecting divider options.
Figure 2. Basic PLL Block Diagram
Table 3. Clock Output Definition
Clock Output Divider Definition and Notes
None Clock output source is the reference input frequency
/DIV1N Clock output uses a generated /DIV1N option from Divider Bank 1. Allowable values for DIV1N are 4 to 127.
If Divider Bank 1 is not being used, set DIV1N to 8.
/2 Clock output uses a fixed /2 option from Divider Bank 1. If this option is used, DIV1N must be divisible by 4.
/3 Clock output uses a fixed /3 option from Divider Bank 1. If this option is used, set DIV1N to 6.
/DIV2N Clock output uses a generated /DIV2N option from Divider Bank 2. Allowable values for DIV2N are 4 to 127.
If Divider Bank 2 is not being used, set DIV2N to 8.
/2 Clock output uses a fixed /2 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 4.
/4 Clock output 2 uses a fixed /4 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 8.
Q
VCO
P
/2
/3
/2
LCLK1
LCLK2
LCLK3
LCLK4
CLK5
CLK6
Crosspoint
Switch
REF
PFD
Divider Bank 1
/4
Divider Bank 2
/DIV1N
/DIV2N
Matrix
[+] Feedback
CY22050,
CY220501
Document #: 38-07006 Rev. *G Page 5 of 10
Reference Crystal Input
The input crystal oscillator of the CY22050 is an important
feature because of the flexibility it allows the user in selecting a
crystal as a reference clock source. The oscillator inverter has
programmable gain, allowing for maximum compatibility with a
reference crystal, based on manufacturer, process,
performance, and quality.
The value of the input load capacitors is determined by eight bits
in a programmable register. Total load capacitance is determined
by the formula:
CapLoad = (C
L
– C
BRD
– C
CHIP
)/0.09375 pF
In CyClocksRT, enter the crystal capacitance (C
L
). The value of
CapLoad is determined automatically and programmed into the
CY22050.
If you require greater control over the CapLoad value, consider
using the CY22150 for serial configuration and control of the
input load capacitors. For an external clock source, the default is
0.
Input load capacitors are placed on the CY22050 die to reduce
external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency shift
that occurs when non-linear load capacitance is affected by load,
bias, supply, and temperature changes.
Absolute Maximum Conditions
Parameter Description Min Max Unit
V
DD
Supply Voltage –0.5 7.0 V
V
DDL
I/O Supply Voltage –0.5 7.0 V
T
S
Storage Temperature
[3]
–65 125 °C
T
J
Junction Temperature 125 °C
Package Power Dissipation—Commercial Temp 450 mW
Package Power Dissipation—Industrial Temp 380 mW
Digital Inputs AV
SS
– 0.3 AV
DD
+ 0.3 V
Digital Outputs referred to V
DD
V
SS
– 0.3 V
DD
+ 0.3 V
Digital Outputs referred to V
DDL
V
SS
– 0.3 V
DDL
+0.3 V
ESD Static Discharge Voltage per MIL-STD-833, Method 3015 2000 V
Recommended Operating Conditions
Parameter Description Min Typ. Max Unit
V
DD
Operating Voltage 3.135 3.3 3.465 V
VDDL
HI
Operating Voltage 3.135 3.3 3.465 V
VDDL
LO
Operating Voltage 2.375 2.5 2.625 V
T
AC
Ambient Commercial Temp 0 70 °C
T
AI
Ambient Industrial Temp –40 85 °C
C
LOAD
Max. Load Capacitance V
DD
/V
DDL
= 3.3V 15 pF
C
LOAD
Max. Load Capacitance V
DDL
= 2.5V 15 pF
f
REFD
Driven REF 1 133 MHz
f
REFC
Crystal REF 8 30 MHz
t
PU
Power up time for all V
DD
s to reach minimum specified
voltage (power ramps must be monotonic)
0.05 500 ms
[+] Feedback
CY22050,
CY220501
Document #: 38-07006 Rev. *G Page 6 of 10
DC Electrical Characteristics
Parameter
[4]
Name Description Min Typ. Max Unit
I
OH3.3
Output High Current V
OH
= V
DD
– 0.5V, V
DD
/V
DDL
= 3.3V 12 24 mA
I
OL3.3
Output Low Current V
OL
= 0.5V, V
DD
/V
DDL
= 3.3V 12 24 mA
I
OH2.5
Output High Current V
OH
= V
DDL
– 0.5V, V
DDL
= 2.5V 8 16 mA
I
OL2.5
Output Low Current V
OL
= 0.5V, V
DDL
= 2.5V 8 16 mA
V
IH
Input High Voltage CMOS levels, 70% of V
DD
0.7 1.0 V
DD
V
IL
Input Low Voltage CMOS levels, 30% of V
DD
00.3V
DD
I
VDD
[5,6]
Supply Current
AV
DD
/V
DD
Current 45 mA
I
VDDL3.3
[5,6]
Supply Current
V
DDL
Current (V
DDL
= 3.465V) 25 mA
I
VDDL2.5
[5,6]
Supply Current
V
DDL
Current (V
DDL
= 2.625V) 17 mA
I
DDS
Power Down Current V
DD
= V
DDL
= AV
DD
= 3.465V 50 μA
I
OHZ
I
OLZ
Output Leakage V
DD
= V
DDL
= AV
DD
= 3.465V 10 μA
AC Electrical Characteristics
Parameter
[4]
Name Description Min Typ. Max Unit
t1 Output frequency,
commercial temp
Clock output limit, 3.3V 0.08 (80 kHz) 200 MHz
Clock output limit, 2.5V 0.08 (80 kHz) 166.6 MHz
Output frequency, indus-
trial temp
Clock output limit, 3.3V 0.08 (80 kHz) 166.6 MHz
Clock output limit, 2.5V 0.08 (80 kHz) 150 MHz
t2 Output duty cycle Duty cycle is defined in Figure 4; t1/t2
f
OUT
> 166 MHz, 50% of V
DD
40 50 60 %
Duty cycle is defined in Figure 4; t1/t2
f
OUT
< 166 MHz, 50% of V
DD
45 50 55 %
t3
LO
Rising edge slew rate
(V
DDL
= 2.5V)
Output clock rise time, 20% – 80% of V
DDL
.
Defined in Figure 5
0.6 1.2 V/ns
t4
LO
Falling edge slew rate
(V
DDL
= 2.5V)
Output clock fall time, 80% – 20% of V
DDL
.
Defined in Figure 5
0.6 1.2 V/ns
t3
HI
Rising edge slew rate
(V
DDL
= 3.3V)
Output clock rise time, 20% – 80% of V
DD
/V
DDL
.
Defined in Figure 5
0.8 1.4 V/ns
t4
HI
Falling edge slew rate
(V
DDL
= 3.3V)
Output clock fall time, 80% – 20% of V
DD
/V
DDL
.
Defined in Figure 5
0.8 1.4 V/ns
t5
[7]
Skew
Output-output skew between related outputs 250 ps
t6
[8]
Clock jitter
Peak-to-peak period jitter (see Figure 6)250ps
t10 PLL lock time 0.30 3 ms
[+] Feedback
P1-P3P4-P6P7-P9P10-P10

CY22050ZXC-134T

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Buy CY22050ZXC-134T
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK GEN PROG 16-TSSOP
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