EVALUATION CIRCUIT (VDD = +5.0 V, VCONT1 to VCONT4 = 0 V/+5.0 V, Pin = 0 dBm, ZO = 50 , DC
Blocking Capacitor = 1 000 pF)
Z
O
= 50
Z
O
= 50
1 000 pF (RF Bypass Condenser)
1 000 pF
(DC Blocking Condenser)
1 000 pF
(DC Blocking Condenser)
1 000 pF
1 000 pF
1 000 pF
V
CONT
4
V
CONT
1
V
CONT
2
V
CONT
3
IN-C
OUT2
OUT1
IN-D
IN-A
V
DD
IN-B
1 000 pF
1 000 pF
1 000 pF
1 000 pF
16
1
9
8
Remark Back Side : GND
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
Data Sheet PU10620EJ01V0DS
5
µ
PD5716GR
ILLUSTRATION OF THE TEST CIRCUIT ASSEMBLED ON EVALUATION BOARD
(Top View) (Bottom View)
C1
C1
C1
C1
C1
C1
C2
C2
C2
C2
C2
Notes
1. 50 × 53 × 0.51 mm double sided copper clad RO4003 (Rogers) board (
ε
r = 3.38).
2. Au plated on pattern
3.
: Through holes
4. C1, C2: 1 000 pF
Data Sheet PU10620EJ01V0DS
6
µ
PD5716GR
TYPICAL CHARACTERISTICS
(T
A = +25°C, VDD = +5.0 V, VCONT = 0 V/+5.0 V, Pin = 0 dBm, ZO = 50 , unless otherwise specified)
–3
–4
–5
–6
–7
–8
–9
–10
0.0 1.0 1.5 2.00.5 2.5 3.0
Insertion Loss L
INS
(dB)
Frequency f (GHz)
INSERTION LOSS vs. FREQUENCY
(INx
-
OUT, all states)
Other mode
On channel mode : AA, BB, CC, DD
0
–10
–20
–30
–40
Input Return Loss RL
in
(dB)
Frequency f (GHz)
INPUT RETURN LOSS vs. FREQUENCY
SIGNAL LEAKAGE (dB)
Frequency f (GHz)
SIGNAL LEAKAGE vs. FREQUENCY
(INx
-
OUT, all states)
Output Return Loss RL
out
(dB)
Frequency f (GHz)
OUTPUT RETURN LOSS vs. FREQUENCY
0.0 1.5 2.01.00.5 2.5 3.0
Input deselected
Input selected
–30
–40
–50
–60
–70
–80
0.0 1.0 1.5 2.00.5 2.5 3.0
0
–10
–20
–30
–40
–50
0.0 1.0 1.5 2.00.5 2.5 3.0
Remark The graphs indicate nominal characteristics.
Data Sheet PU10620EJ01V0DS
7
µ
PD5716GR

UPD5716GR-E1-A

Mfr. #:
Manufacturer:
CEL
Description:
IC MMIC 4X2 IF SWITCH MATRIX
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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