SJA1105 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 7 November 2016 2 of 34
NXP Semiconductors
SJA1105
5-port automotive Ethernet switch
Ingress rate-limiting on a per-port and per-priority basis for Unicast/Multicast and
Broadcast traffic
Frame replication and retagging of traffic
Frame mirroring for enhanced diagnostics
Hardware support for IEEE 802.1AS and IEEE 802.1Qav for AVB traffic support
Ingress and egress timestamping per port
Ten IEEE 802.1Qav credit-based shapers available; shapers can be freely allocated to
any priority queue on a per port basis
Support for AVB SR Class A, Class B and Class C traffic
IEEE 1588v2 one-step sync forwarding in hardware
IEEE 802.1X support for setting port reachability and disabling address learning
Broadcast storm protection
Statistics for dropped frames and buffer load
2.3 TT and TSN features (SJA1105TEL only)
IEEE 802.1Qbv time-aware traffic
IEEE 802.1Qci per-stream policing (pre-standard)
Support for ring-based redundancy (for time-triggered traffic only)
1024 deterministic Ethernet flows with per-flow based:
Time-triggered traffic transmission
Ingress policing and reception window check
Active and redundant routes
Statistics
2.4 Interface features
MII/RMII interfaces supporting all standard Ethernet PHY technologies such as (but
not limited to) Fast Ethernet (IEEE 100BASE-TX), IEEE 100BASE-T1 and optical
PHYs
RGMII for interfacing with Gigabit Ethernet (1000BASE-T) PHYs (Gigabit Ethernet;
Ref. 4
)
MAC and PHY modes for interfacing (MII/RMII/RGMII) directly with another switch or
host processor
Programmable drive strength for all interfaces
SPI at up to 25 MHz for host processor access
2.5 Other features
25 MHz system clock input from crystal oscillator or AC-coupled single-ended clock
25 MHz reference clock output
Device reset input from host processor
IEEE 1149.1 compliant JTAG interface for TAP controller access and boundary scan
